MCX A34 Mixed-Signal, Optimized for Motor Control and High-Performance Analog Peripherals

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MCX A345 and A346 MCUs

MCX A343 and A346 MCUs Block Diagram

MCX A343 and A344 MCUs

MCX A343 and A344 MCUs Block Diagram

Features

Core Platform

  • Arm® Cortex®-M33 180 MHz

Processing Accelerators

  • MAU (Math Accelerate Unit), supports trigonometric, reciprocal, square, square root, sine, cosine and arctan algorithms
  • SmartDMA, co-processor for applications such as parallel camera interface and keypad scanning

Memory

  • Single-bank flash
    • Up to 256 KB Flash with ECC (support one bit correction and two bits detection)
  • Cache engine with 8 kB RAM
  • Up to 64 KB RAM of which 8 KB is shared with cache, configurable as up to 8 KB RAM with ECC (support one bit correction and two bits detection)
  • All RAM can be retained down to deep power Down mode
  • ROM

Peripherals

  • Analog
    • 2x 16-bit ADC
      • Up to 3 Msps in 16-bit mode, and 3.75 Msps in 12-bit mode
      • Up to 39 ADC input channels total (depending on the package)
      • Integrated temperature sensor
    • 3x High-speed Comparators with 8 input pins and 8-bit DAC as internal reference
      • 1x LPCMP is functional down to deep power down mode
    • 3 x high-speed comparators with 8 input pins and 8-bit DAC as internal reference
      • 1 x LPCMP is functional down to deep power down mode
    • 3x OPAMP without PGA
  • Advanced Motor Control Subsys
    • Up to 2x FlexPWM each with 4 submodules, providing 16 complementary outputs of PWM (no Nanoedge module)
    • Up to 2x Quadrature Encoder/Decoder (eQDC)
    • 2x AOI (AND/OR/Invert) module support up to 4 output trigger
  • Timers
    • 3 x 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests
    • Low power timer
    • Frequency measurement timer
    • Windowed watchdog timer
    • Wake timer
    • Micro-tick timer (UTICK)
    • OS event timer
    • RTC timer without external 32KHz input
  • Communication Interfaces for Connectivity
    • 2x LPSPI, 2x LPI2C, 4x LPUART
    • 1x FlexCAN with FD

Security

  • 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version5 specification
  • Device lifecycle management
  • Flash read/write/execute permission protect by MBC and lockable
  • Implicit-protected flash region (IFR)
  • Security monitoring
    • Code Watchdog for code flow integrity checking
    • GLIKEY enhances protection against attacks to gain unauthorized access to sensitive registers

Packaging

  • LQFP100 14x14mm, LQFP64 10x10mm, LQFP48 7x7mm, QFN32 5x5mm

MCUXpresso Developer Experience

Features Table

Main Clock Flash Features Packages FRDM Board
MCXA343  180 MHz 128 KB
  • 2x 16 bit ADC w/ 3.0 Msps
  • Up to 3x OpAmp w/o PGA
  • HVQFN32
  • LQFP48
  • LQFP64
  • LQFP100
FRDM-MCXA344 
MCXA344  180 MHz 256 KB
  • 2x 16 bit ADC w/ 3.0 Msps
  • Up to 3x OpAmp w/o PGA
  • HVQFN32
  • LQFP48
  • LQFP64
  • LQFP100
FRDM-MCXA344 
MCXA345 180 MHz 512 KB
  • 4x 16 bit ADC w/ 3.2 Msps
  • 1x 12 bit DAC
  • Up to 4x OpAmp w/o PGA
  • LQFP64
  • LQFP100
  • LQFP144
  • WFBGA169
FRDM-MCXA346
MCXA346 180 MHz 1024 KB
  • 4x 16 bit ADC w/ 3.2 Msps
  • 1x 12 bit DAC
  • Up to 4x OpAmp w/o PGA
  • LQFP64
  • LQFP100
  • LQFP144
  • WFBGA169
FRDM-MCXA346

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