MCX A35: Arm® Cortex®-M33 Mixed-Signal MCUs for Advanced Motor Control at 240 MHz

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MCX A355 and A356

MCX A355 and A356: Arm® Cortex®-M33-Based Microcontrollers

Features

Core Platform

  • Arm® Cortex®-M33 240 MHz

Processing Accelerators

  • MAU (Math Accelerate Unit), supports trigonometric, reciprocal, square, square root, sine, cosine and arctan algorithms
  • SmartDMA, coprocessor for applications such as parallel camera interface and keypad scanning

Memory

  • Single-bank Flash: Up to 1024 kB Flash with ECC (supports one bit correction and two-bit detection)
  • Cache Engine with 8 kB RAM
  • Up to 256 kB RAM of which 8 kB is shared with cache, configurable as up to 8 kB RAM with ECC (support one bit correction and two-bit detection)
  • All RAM can be retained down to Deep Power-down mode
  • ROM

Peripherals

  • Advanced Motor Control
    • 2x FlexPWM each with 4 submodules, providing 16 complementary outputs of PWM (no Nanoedge module)
    • 2x Quadrature Encoder/Decoder (eQDC)
    • support up to 4 output triggers
    • Analog
      • 4x 16-bit ADC
        • 3.2 Msps in 16-bit mode, and 4 Msps in 12-bit mode
        • Up to 82 ADC Input channels total (depending on the package)
        • Integrated temperature sensor
      • 1x 12-bit DAC
        • Up to 1 Msps
      • 3x High-speed Comparators with 8 input pins and 8-bit DAC as internal reference
        • 1x LPCMP is functional down to Deep Power-down mode
      • 4x OPAMP without PGA
    • Timers
      • 5x 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode and external count input. Specific timer events can be selected to generate DMA requests.
      • Low power timer
      • Frequency measurement timer
      • Windowed watchdog timer
      • Wake timer
      • Micro-tick timer (UTICK)
      • OS event timer
      • RTC timer without external 32 KHz input
    • Communication Interfaces for Connectivity
      • 2x LPSPI, 4x LPI2C, 6x LPUART
      • 1x FlexCAN with FD

Security

  • 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version 5 specification
  • Device life cycle management
  • Flash read/write/execute permission protect by MBC and lockable
  • Implicit-protected Flash Region (IFR)
  • Security Monitoring
    • Code watchdog for code flow integrity checking
    • Glitch attack resistant keyed access (Glikey) to security sensitive registers
    • 6x Passive anti-tamper detect

Packaging

  • WFBGA169 7x7 mm, LQFP144 20x20 mm, LQFP100 14x14 mm, LQFP64 10x10 mm

Security

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