Question 1

What is the part family nomenclature for the NAFExx388 family?

Accepted Answer

Below is the nomenclature of the N-AFE family of devices: N-AFE [1: Low power / 7: High speed] [1: No VIEX / 3: VIEX] [1: No Cal (calibrated) / 3: Factory calibrated] [4: 16 bit / 8: 24 bit] [4: 4-ch (channel) / 8: 8-ch (channel)]. The low-power flavor has a max data rate of 288 ksps while the high-speed version can support up to 576 ksps in Normal Settling mode. Refer to the data sheet or contact an NXP sales representative for available part numbers.

Question 2

What are the different input ranges that N-AFE can measure?

Accepted Answer

The N-AFE has eight selectable PGA gain settings of 0.2 V/V to 16 V/V that provide eight differential input full-scale ranges from ±25 V to ±312.5 mV for a variety of applications. In general, all of the HV input characteristics are specified to the linear (nominal) input ranges for all of the channel gain settings, which is 80% of the full input range. Nominal range values (Bipolar DIFF): PGA 0.2=±20 V, 0.4=±10 V, 0.8=±5 V, 1=±4 V, 2=±2 V, 4=±1 V, 8=±0.5 V, 16=±0.25 V. Min and max values (Bipolar DIFF): PGA 0.2=±25 V, 0.4=±12.5 V, 0.8=±6.25 V, 1=±5 V, 2=±2.5 V, 4=±1.25 V, 8=±0.625 V, 16=±0.3125 V.

Question 3

How does the N-AFE implement cancelation of the wire resistance in a 3-wire RTD configuration?

Accepted Answer

Contrary to competitor solutions that implement two matched current generators to cancel the RTD wire resistance, the N-AFE utilizes the integrated current generator (VIEX) with low-temperature drift performance of 4 ppm/°C typical. The N-AFE optimizes the number of RTDs that can be connected to a single chip by using a single-current source allowing four 3-wire RTD measurements with a single chip.

Question 4

What is the difference between user calibration and factory calibration?

Accepted Answer

The user calibration is the process by which the N-AFE is calibrated when it is already mounted on a PCB. The factory calibration is performed during chip manufacturing at the NXP factory. The user calibration achieves overall better accuracy with a typical TUE of ±0.002% of full scale at room temperature. This is because all the errors introduced by external components and the soldering process are calibrated too. However, the accuracy guaranteed by the factory calibrated part, which is ±0.06% of full scale at room, allows our customers to avoid the expensive and time-consuming calibration process if the provided accuracy fits their requirements.

Question 5

Which register pointers should be used to utilize the factory calibration coefficients for NAFExx388?

Accepted Answer

The factory calibration is performed for all 8 PGA gain settings (input ranges) and the coefficients are stored in separate registers. Gain/OS coefficient pointer of 0, 1, 2, …, 7 should be used for Gain_code=0, 1, 2, …, 7 respectively for datasheet specified measurement accuracy. Please refer to Table 12 in the datasheet NAFE13388.

Question 6

How fast can the N-AFE read in the Single-Channel Conversion mode?

Accepted Answer

The N-AFE is available in both a low-power (LP) version and a high-speed (HS) version with maximum data rates of 288 ksps and 576 ksps respectively. The single-channel conversion with normal settling provides the fastest readout of 3.472 us for the LP (NAFE1x388) version and 1.738 us for the HS (NAFE7x388) version.

Question 7

How fast can the N-AFE read in Multichannel conversion mode?

Accepted Answer

When in Multichannel Conversion mode, the ADC input signal path requires 16.4 us and 8.2 us front-end settling time (Tswitch) for NAFE1x388 and NAFE7x388 respectively. The user should use single-cycle settling for multichannel readout to avoid settling errors. The ADC data rate in single-cycle settling mode is a quarter of the data rate in Normal Settling mode (72 ksps and 144 ksps for LP and HS parts respectively). Code 17 for channel programmable delay meets the Tswitch requirement in both flavors. NAFE1x388 fastest eight-channel read time = 8 * (13.88 us + 16.49 us) ≈ 240 us (30 us/channel). NAFE7x388 fastest eight-channel read time = 8 * (6.94 us + 8.24 us) ≈ 120 us (15 us/channel).

Question 8

How well can N-AFE reject 50/60 Hz line frequency?

Accepted Answer

The NAFE13388 features a digital filter that provides a 50 Hz and 60 Hz Normal mode rejection (NMR) at lower data rates. The SINC4 filter provides NMR at data rates of 10 sps, 50 sps and 60 sps.

Question 9

What is the 50/60 Hz common-mode rejection (CMRR) at speeds higher than 100 sps?

Accepted Answer

The N-AFE provides more than 110 dB CMRR at data rates much higher than 60 sps (without 50/60 Hz rejection of notch filter).

Question 10

What are the NAFExx388's Crosstalk (CT) specifications and conditions?

Accepted Answer

Static crosstalk: ±1 µV/V. Dynamic crosstalk (not AC spec): ±1 µV/V. Test conditions: 1) Input crosstalk DC (single channel): Set the target channel at 0 V and vary the main channel from 0 V to 10 V (and -10 V) using single-channel conversion. 2) Input crosstalk dynamic (multichannel, not an AC crosstalk): Set the target channel to -10 V and the adjacent main channel from 0 V to 10 V using multichannel conversion. This quantifies the effect of the channel path settling (MUX+PGA) at specified DR0 and CH_delay in condition for a worst-case input swing at the ADC input.

Question 11

What is the NAFE33352 and what are its primary applications?

Accepted Answer

The NAFE33352 is a software-configurable universal low-power Analog Input/Output Analog Front End (AIO-AFE) designed for high-precision measurement and control in industrial applications. It is used in PLCs, DCS I/O modules, data acquisition systems and industrial automation.

Question 12

What types of analog signals can the NAFE33352 handle?

Accepted Answer

It supports voltage, current, resistance, temperature (RTD, thermocouple), load cell inputs and voltage and current outputs, with software-configurable ranges and modes.

Question 13

What are the supported DAC output modes in the NAFE33352?

Accepted Answer

The DAC supports three output modes: High-Z mode, Voltage-output mode and Current-output mode. These are controlled via the AO_MODE register and associated control bits for enabling voltage or current source amplifiers.

Question 14

What are the key features of the NAFE33352's ADC and DAC?

Accepted Answer

The device includes a 14/16/18-bit DAC and a 16/24-bit ADC. The ADC supports data rates from 7.5 sps to 288 ksps, and the DAC supports up to 100 ksps. It offers ±0.005% ADC accuracy at room temperature and ±0.02% over temperature.

Question 15

What is the purpose of the Auto-DAC waveform generator?

Accepted Answer

The Auto-DAC waveform generator allows the device to autonomously generate waveforms (e.g., sine, triangle) based on user-defined amplitude, frequency and step size parameters. It is useful for test and calibration routines.

Question 16

How does the NAFE33352 handle DAC slew rate control?

Accepted Answer

The device includes a programmable slew rate control feature that allows users to limit the rate of change of the DAC output. This is useful for avoiding overshoot or overcurrent in capacitive or inductive loads.

Question 17

What calibration options are available for the NAFE33352?

Accepted Answer

The device supports both factory and user calibration. It includes non-volatile memory for storing calibration coefficients and allows self-calibration without external equipment.

Question 18

Which register pointers should be used to utilize the factory calibration coefficients for Analog Output and Analog Input modes in NAFE33352?

Accepted Answer

The factory calibration is performed for all four modes of operations – Voltage Output, Current Output, Voltage Input and Current Input. These coefficients are stored in separate registers and Table 39 from the NAFE33352 datasheet shows their respective pointers.

Question 19

How does the device ensure signal integrity and protection?

Accepted Answer

It includes low-drift voltage references, low-offset buffers, high-voltage amplifiers with 70 V input protection, and advanced diagnostic circuits for fault detection and predictive maintenance, which includes open/short detection, voltage rail monitoring, temperature sensing and programmable alarms for over/under range and overtemperature conditions.

Question 20

How does the device handle protections when in output mode?

Accepted Answer

It features dual protection mechanisms for voltage and current output modes, including fast-reaction short-circuit protection and programmable overload protection with configurable thresholds and timers.

Question 21

What are the thermal and electrical operating limits of the NAFE33352?

Accepted Answer

It operates from -40 °C to 125 °C, with a junction temperature limit of 150 °C. It supports ±36 V protection at the I/O terminals and has robust ESD ratings (HBM ±4500 V, CDM ±750 V).

Question 22

What communication interface does the NAFE33352 use?

Accepted Answer

It uses a 4-wire SPI interface (CSB, SCLK, MOSI, MISO) with optional CRC for data integrity and speed up to 32 MHz. It also includes SYNC and DRDY pins for synchronization and data readiness signaling.

Question 23

How does the device support synchronization in multi-AFE systems?

Accepted Answer

The SYNC pin allows synchronization of multiple NAFE33352 devices. A rising edge on SYNC can trigger simultaneous conversions across devices, ensuring coherent sampling.

Question 24

What are the available reading modes for data acquisition?

Accepted Answer

The NAFE33352 supports five reading modes: Single-Channel Single-Reading (SCSR), Single-Channel Continuous-Reading (SCCR), Multichannel Single-Reading (MCSR), Multichannel Multireading (MCMR), and Multichannel Continuous-Reading (MCCR).

Question 25

How to debug a non-operational Analog Output in NAFE33352?

Accepted Answer

Use the following checklist to diagnose why the Analog Output (AO) is not functioning as expected: 1) The REFDACBUF on NAFE33352 is disabled by default on power up. Enable it by setting AO_SYSCFG.DAC_SEL_REFBUF_ON=11b. Without this, the DAC output will remain inactive. 2) When writing AO data over SPI, the device requires a minimum TDAC_wait time between the last SCLK edge and CSB rising edge. As shown in Figure 42 of the datasheet, this delay must be 18 system clock periods. For the NAFE33352, the system clock period is 217 ns, resulting in a TDAC_wait time of 3.9 µs. For the high speed NAFE93352, this wait time is half as long - 1.95 µs. 3) Figure 42 also specifies that the 18-bit DAC code must be left aligned within the 24-bit SPI data frame. Misalignment will result in incorrect analog output. 4) Read the AIO_STATUS register to determine whether the device has detected AO overload or AO short-circuit. If a fault is detected, the device forces AO_STATUS = Hi Z, placing the analog output in high impedance mode. To recover, perform a soft reset or hard reset after correcting the fault condition.

Question 26

What package and ordering options are available for the NAFE33352?

Accepted Answer

The device comes in a 6 mm x 6 mm 40-pin HVQFN package. Ordering options include reel and tray formats with part numbers like NAFE33352B40BSMP and NAFE33352B40BSE respectively.

额定范围值(V)
类型	PGA增益设置
类型	0.2	0.4	0.8	1	2	4	8	16
双极DIFF	±20.00000	±10.00000	±5.00000	±4.00000	±2.00000	±1.00000	±0.50000	±0.25000
双极SE	±10.00000	±5.00000	±2.50000	±2.00000	±1.00000	±0.50000	±0.25000	±0.12500
单极DIFF	±10.00000	±5.00000	±2.50000	±2.00000	±1.00000	±0.50000	±0.25000	±0.12500
单极SE	±10.00000	±5.00000	±2.50000	±2.00000	±1.00000	±0.50000	±0.25000	±0.12500

最小和最大值(V)
类型	PGA增益设置
类型	0.2	0.4	0.8	1	2	4	8	16
双极DIFF	±25.00000	±12.50000	±6.25000	±5.00000	±2.50000	±1.25000	±0.62500	±0.31250
双极SE	±12.50000	±6.25000	±3.12500	±2.50000	±1.25000	±0.62500	±0.31250	±0.15625
单极DIFF	±12.50000	±6.25000	±3.12500	±2.50000	±1.25000	±0.62500	±0.31250	±0.15625
单极SE	±12.50000	±6.25000	±3.12500	±2.50000	±1.25000	±0.62500	±0.31250	±0.15625

分辨率(V)
类型	PGA增益设置
类型	0.2	0.4	0.8	1	2	4	8	16
双极DIFF	3.0E-6	1.5E-6	745.1E-9	596.0E-9	298.0E-9	149.0E-9	74.5E-9	37.3E-9
双极SE	3.0E-6	1.5E-6	745.1E-9	596.0E-9	298.0E-9	149.0E-9	74.5E-9	37.3E-9
单极DIFF	3.0E-6	1.5E-6	745.1E-9	596.0E-9	298.0E-9	149.0E-9	74.5E-9	37.3E-9
单极SE	3.0E-6	1.5E-6	745.1E-9	596.0E-9	298.0E-9	149.0E-9	74.5E-9	37.3E-9

满量程(V)
类型	PGA增益设置
类型	0.2	0.4	0.8	1	2	4	8	16
双极DIFF	50	25	12.5	10	5	2.5	1.25	0.625
双极SE	25	12.5	6.25	5	2.5	1.25	0.625	0.3125
单极DIFF	25	12.5	6.25	5	2.5	1.25	0.625	0.3125
单极SE	12.5	6.25	3.125	2.5	1.25	0.625	0.3125	0.15625

模拟前端

输入模拟前端

NAFEB43388 新

输入/输出模拟前端

NAFE33352 新

NAFE33350 新

NAFE33350全集成通用AO-AFE

评估板和参考设计

模拟前端常见问题解答

通用完全可配置模拟输入/输出前端

设计资源

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