QorIQ® P3041四核通信处理器

P3041 停产

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QorIQ® P3041处理器是一款优化的四核设备，采用P4平台上领先的架构功能。它基于Power Architecture®技术，适用于大部分与P4平台处理器相同的应用，且提供更加高性价比的解决方案。

P3041具有P4平台的功能，例如可缩短延迟时间的三级缓存、支持可靠虚拟化的硬件管理程序、减轻内核处理数据包的负担的数据通路加速架构，以及消除内部瓶颈的CoreNet®交换结构等。这使P3041架构可与P4平台以及采用相同架构的P5平台兼容。P3041与P4040、P4080、P5010和P5020引脚兼容。

产品详情

框图

P3041 BDIMG

QorIQ P3041 Quad-Core Communications Processors
获取框图PDF

特征

内核复合体

  • 4个高性能e500mc内核，运行频率高达1.5 GHz
  • 三级缓存：32 KB I/D L1; 每内核128 KB专用L2; 1 MB共享CorNet平台缓存

网络元件

  • 1个10 Gbps以太网(XAUI)控制器
  • 5个1 Gbps以太网控制器，在SGMII、2.5 Gbps SGMII或RGMII上提供

加速器和存储器控制

  • 64位(72位，带ECC) DDR2/3存储器控制器，数据频率高达1.3 GHz
  • DPAA采用加速技术，适用于以下功能
    • 数据包解析、分类和分发
    • 支持队列管理，可进行调度、数据包排序和阻塞管理
    • 支持硬件缓冲管理，可缓冲分配和取消分配
    • 加密(SEC 4.2)
    • RegEx模式匹配(PME 2.1)

基本外设和互连

  • 高速外设接口：
    • 4个PCI Express® v2.0控制器/端口，运行频率高达5 GHz
    • 两个串行RapidIO® 1.3/2.1控制器/端口，运行频率高达5 GHz，支持9和11类消息传递
    • 两个SATA 2.0接口
    • 2个带有集成式PHY的USB 2.0控制器、增强型本地总线控制器(eLBC)、SD/MMC、SPI控制器、4个I²C控制器、2个双UART(DUART)、多核可编程中断控制器(PIC)、2个4通道DMA引擎

其他特性

  • 硬件管理程序，在内核之间进行安全的操作系统分区
  • 可信引导功能，确保只有正确的代码被引导，且代码不能反向工程
  • 引脚和软件与P4040、P4080、P5010和P5020兼容。

对比表

P2040 P2041 P3041
内核 4x e500mc 4x e500mc 4x e500mc
内核频率 667 - 1200 MHz 1200 - 1500 MHz 1200 - 1500 MHz
L2缓存 - 128KB/内核 128KB/内核
CoreNet平台缓存 1MB前端 1MB前端 1MB前端
DDR 1个64位DDR3/3L 1个64位DDR3/3L 1个64位DDR3/3L
GbE 5 x 1 GbE 5 x 1 GbE + 1 x 10 GbE 5 x 1 GbE + 1 x 10 GbE
PCIe Gen 2.0 3个Gen 2.0控制器5.0GHz 3个Gen 2.0控制器5.0GHz 4个Gen 2.0控制器5.0GHz
USB 2.0 2 2 2
sRIO 1.2 2 2 2
其他接口 2个SATA，2个4通道DMA引擎，4个2引脚UART或2个4引脚UART 2个SATA，2个4通道DMA引擎，4个2引脚UART或2个4引脚UART 2个SATA，2个4通道DMA引擎，4个2引脚UART或2个4引脚UART
加速器 SEC4.2, PME 2.0 SEC4.2, PME 2.0 SEC4.2, PME 2.0

购买/参数

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N true 0 PSPP3041zh 44 产品简介 Product Brief t532 1 参考手册 Reference Manual t877 5 工程设计要点 Technical Notes t521 1 应用笔记 Application Note t789 23 应用笔记软件 Application Note Software t783 1 手册 Brochure t518 2 支持信息 Supporting Information t531 2 数据手册 Data Sheet t520 1 用户指南 User Guide t792 1 白皮书 White Paper t530 5 简介 Fact Sheet t523 2 zh 4 1 1 English The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. 1316699641906701481590 PSP 758.9 KB None None documents None 1316699641906701481590 /docs/en/brochure/P2P3P5APPBRF.pdf 758908 /docs/en/brochure/P2P3P5APPBRF.pdf P2P3P5APPBRF N N 2016-10-31 QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf /docs/en/brochure/P2P3P5APPBRF.pdf Brochure N Y 712453003803778552 2022-12-07 pdf N en Sep 14, 2012 Brochure t518 手册 Brochure N QorIQ P2040/P2041, P3 and P5 Series - Brochures 2 3 English The QorIQ<sup>&#174;</sup> P3041 processor is an optimized, quad-core device built on Power Architecture&#174; technology. The P3041 processor is designed to offer customers a more power- and cost-efficient solution over the P4 product family. 1276547653279726131905 PSP 376.9 KB None None documents None 1276547653279726131905 /docs/en/fact-sheet/QP3041FS.pdf 376879 /docs/en/fact-sheet/QP3041FS.pdf QP3041FS N N 2016-10-31 QorIQ P3041 - Fact Sheet /docs/en/fact-sheet/QP3041FS.pdf /docs/en/fact-sheet/QP3041FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Apr 21, 2014 Fact Sheet t523 简介 Fact Sheet N QorIQ P3041 - Fact Sheet 3 0 English The P3041DS is a flexible development&#13;&#10;system supporting the quad-core P3041&#13;&#10;device. With its 1.5 GHz P3041 and rich&#13;&#10;input/output (I/O) mix, the board is intended&#13;&#10;for development of P3041 in networking and&#13;&#10;Ethernet-centric applications, such as control&#13;&#10;plane and mixed control plane/data plane&#13;&#10;in switches, routers, base station network&#13;&#10;interface cards, aerospace and defense and&#13;&#10;factory automation. 1316723359847701674311 PSP 378.1 KB None None documents None 1316723359847701674311 /docs/en/fact-sheet/P3041DSFS.pdf 378088 /docs/en/fact-sheet/P3041DSFS.pdf P3041DSFS N N 2016-10-31 P3041 Development System /docs/en/fact-sheet/P3041DSFS.pdf /docs/en/fact-sheet/P3041DSFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Sep 22, 2011 Fact Sheet t523 简介 Fact Sheet N P3041 Development System 4 1 English Security continues to be an increasingly important concern in the design of modern systems. Threats against networks and network-connected&#13;&#10;devices are real and growing. With an estimated $40 billion (USD)* of data loss per year, service providers and end-users are becoming painfully&#13;&#10;aware of the consequences of unsecured networks and databases. 1317136062337713598350 PSP 494.4 KB None None documents None 1317136062337713598350 /docs/en/white-paper/QORIQSECBOOTWP.pdf 494394 /docs/en/white-paper/QORIQSECBOOTWP.pdf QORIQSECBOOTWP N N 2016-10-31 Secure Boot - White Paper /docs/en/white-paper/QORIQSECBOOTWP.pdf /docs/en/white-paper/QORIQSECBOOTWP.pdf White Paper N Y 918633085541740938 2023-06-19 pdf N en Jan 25, 2013 White Paper t530 白皮书 White Paper N Secure Boot - White Paper false zh zh 数据手册 Data Sheet 1 5 2 English This document describes the electrical characteristics of the P3041. 1339783482524703861868 PSP 2.8 MB Registration without Disclaimer None documents Extended 1339783482524703861868 /secured/assets/documents/en/data-sheet/P3041EC.pdf 2829137 /secured/assets/documents/en/data-sheet/P3041EC.pdf P3041EC documents Y N 2016-10-31 P3041 QorIQ Integrated Processor Hardware Specifications /webapp/Download?colCode=P3041EC&lang_cd=zh /secured/assets/documents/en/data-sheet/P3041EC.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Feb 22, 2013 980000996212993340 Data Sheet N P3041 QorIQ Integrated Processor Hardware Specifications 参考手册 Reference Manual 5 6 4 English P3041 can be used for combined control, datapath, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing&#13;&#10;systems. 1320688668486717938373 PSP 17.6 MB Registration without Disclaimer None documents Extended 1320688668486717938373 /secured/assets/documents/en/reference-manual/P3041RM.pdf 17622084 /secured/assets/documents/en/reference-manual/P3041RM.pdf P3041RM documents Y N 2016-10-31 P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual /webapp/Download?colCode=P3041RM&lang_cd=zh /secured/assets/documents/en/reference-manual/P3041RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 11, 2016 500633505221135046 Reference Manual N P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual 7 3 English E500MCRM: The e500mc core is a low-power implementation of the resources for embedded processors defined by the Power ISA &#8482;. The core is a 32-bit implementation and implements 32 32-bit general-purpose registers; however it supports accesses to 36-bit physical addresses 1317141680002726866677 PSP 5.3 MB None None documents None 1317141680002726866677 /docs/en/reference-manual/E500MCRM.pdf 5320755 /docs/en/reference-manual/E500MCRM.pdf E500MCRM documents N N 2016-10-31 E500MCRM, e500mc Core Reference Manual with Updates /docs/en/reference-manual/E500MCRM.pdf /docs/en/reference-manual/E500MCRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Jul 9, 2015 500633505221135046 Reference Manual N E500MCRM, e500mc Core Reference Manual with Updates 8 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM&lang_cd=zh /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 9 2 English This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. 1301610099994679235703 PSP 19.4 MB Registration without Disclaimer None documents Extended 1301610099994679235703 /secured/assets/documents/en/reference-manual/DPAARM.pdf 19426366 /secured/assets/documents/en/reference-manual/DPAARM.pdf DPAARM documents Y N 2016-10-31 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /webapp/Download?colCode=DPAARM&lang_cd=zh /secured/assets/documents/en/reference-manual/DPAARM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Nov 4, 2011 500633505221135046 Reference Manual Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual 10 0 English 1319838519472711002442 PSP 7.0 MB Registration without Disclaimer None documents Extended 1319838519472711002442 /secured/assets/documents/en/reference-manual/P3041SECRM.pdf 6991784 /secured/assets/documents/en/reference-manual/P3041SECRM.pdf P3041SECRM documents Y N 2016-10-31 P3041 Security (SEC 4.2) Reference Manual /webapp/Download?colCode=P3041SECRM&lang_cd=zh /secured/assets/documents/en/reference-manual/P3041SECRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Oct 28, 2011 500633505221135046 Reference Manual N P3041 Security (SEC 4.2) Reference Manual 应用笔记 Application Note 23 11 0 English AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. 1464124094029726989039 PSP 401.8 KB None None documents None 1464124094029726989039 /docs/en/application-note/AN5295.pdf 401764 /docs/en/application-note/AN5295.pdf AN5295 documents N N 2016-10-31 AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf /docs/en/application-note/AN5295.pdf Application Note N 645036621402383989 2022-12-07 pdf N en May 24, 2016 645036621402383989 Application Note N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 12 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 13 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 14 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 15 Rev 0 English AN4403: This document provides recommendations for new designs based on the P3041. 1398358439319724308174 PSP 494.2 KB None None documents None 1398358439319724308174 /docs/en/application-note/AN4403.pdf 494196 /docs/en/application-note/AN4403.pdf AN4403 documents N N 2016-10-31 AN4403, P3041 QorIQ Integrated Processor Design Checklist - Application Notes /docs/en/application-note/AN4403.pdf /docs/en/application-note/AN4403.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 24, 2014 645036621402383989 Application Note N AN4403, P3041 QorIQ Integrated Processor Design Checklist - Application Notes 16 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=zh /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 17 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 18 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=zh /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 19 1 English This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. 1329517560294722281831 PSP 216.6 KB None None documents None 1329517560294722281831 /docs/en/application-note/AN4375.pdf 216552 /docs/en/application-note/AN4375.pdf AN4375 documents N N 2016-10-31 QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf /docs/en/application-note/AN4375.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 21, 2012 645036621402383989 Application Note N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 20 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 21 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=zh /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 22 0 English This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. 1301697264409722558859 PSP 648.7 KB Registration without Disclaimer None documents Extended 1301697264409722558859 /secured/assets/documents/en/application-note/AN4290.pdf 648695 /secured/assets/documents/en/application-note/AN4290.pdf AN4290 documents Y N 2016-10-31 Configuring the Data Path Acceleration Architecture (DPAA) /webapp/Download?colCode=AN4290&lang_cd=zh /secured/assets/documents/en/application-note/AN4290.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 1, 2011 645036621402383989 Application Note N Configuring the Data Path Acceleration Architecture (DPAA) 23 0 English 1287581868481730872047 PSP 142.0 KB None None documents None 1287581868481730872047 /docs/en/application-note/AN3423.pdf 141965 /docs/en/application-note/AN3423.pdf AN3423 documents N 2016-10-31 Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf /docs/en/application-note/AN3423.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 6, 2010 645036621402383989 Application Note N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 24 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=zh /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 25 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 26 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 27 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 28 1 English Application Note 1060017730134725666689 PSP 612.9 KB None None documents None 1060017730134725666689 /docs/en/application-note/AN2490.pdf 612895 /docs/en/application-note/AN2490.pdf AN2490 documents N 2016-10-31 MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf /docs/en/application-note/AN2490.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 23, 2009 645036621402383989 Application Note N MPC603e and e500 Register Model Comparison 29 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869&lang_cd=zh /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 30 1.0 English This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. 1208458263255715391554 PSP 505.7 KB None None documents None 1208458263255715391554 /docs/en/application-note/AN3550.pdf 505720 /docs/en/application-note/AN3550.pdf AN3550 documents N 2016-10-31 Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf /docs/en/application-note/AN3550.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 22, 2008 645036621402383989 Application Note N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 31 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 32 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 33 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 用户指南 User Guide 1 34 1 Y English https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y 1576719019599707128294 PSP None None documents None 1576719019599707128294 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC SPECTRE-MELTDOWN-POWER-ISA-DOC documents N N Y 2019-12-18 Spectre and Meltdown Updates for Power ISA Cores https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC User Guide N 132339537837198660 Y /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html 2022-12-07 N en Nov 14, 2019 132339537837198660 User Guide Y N Spectre and Meltdown Updates for Power ISA Cores 应用笔记软件 Application Note Software 1 35 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies 手册 Brochure 1 36 0 English 1326753923169722820717 PSP 477.8 KB None None documents None 1326753923169722820717 /docs/en/brochure/PWRARBYNDBITSTA.pdf 477805 /docs/en/brochure/PWRARBYNDBITSTA.pdf PWRARBYNDBITSTA documents N 2016-10-31 Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) /docs/en/brochure/PWRARBYNDBITSTA.pdf /docs/en/brochure/PWRARBYNDBITSTA.pdf Brochure N 712453003803778552 2022-12-07 pdf en Feb 7, 2012 712453003803778552 Brochure N Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) 工程设计要点 Technical Notes 1 37 0 English Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices 1299186935006725024525 PSP 492.6 KB Registration without Disclaimer None documents Extended 1299186935006725024525 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 492591 /secured/assets/documents/en/engineering-bulletin/EB739.pdf EB739 documents Y N 2016-10-31 COM Express Pin Assignments for QorIQ Devices /webapp/Download?colCode=EB739&lang_cd=zh /secured/assets/documents/en/engineering-bulletin/EB739.pdf Technical Notes N 389245547230346745 2022-12-07 pdf Y en Mar 3, 2011 389245547230346745 Technical Notes N COM Express Pin Assignments for QorIQ Devices 产品简介 Product Brief 1 38 0 English This document provides an overview of the P3041 QorIQ<sup>&#174;</sup> communications processor features as well as application use cases. 1321648686150710474517 PSP 334.3 KB None None documents None 1321648686150710474517 /docs/en/product-brief/P3041PB.pdf 334333 /docs/en/product-brief/P3041PB.pdf P3041PB documents N N 2016-10-31 P3041 QorIQ Communications Processor Product Brief /docs/en/product-brief/P3041PB.pdf /docs/en/product-brief/P3041PB.pdf Product Brief N 899114358132306053 2023-06-19 pdf N en Nov 18, 2011 899114358132306053 Product Brief N P3041 QorIQ Communications Processor Product Brief 支持信息 Supporting Information 2 39 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 40 1 English 1292347734027724236696 PSP 150.0 KB None None documents None 1292347734027724236696 /docs/en/supporting-information/P3041PECI.pdf 149978 /docs/en/supporting-information/P3041PECI.pdf P3041PECI documents N N 2016-10-31 P3041 Family Customer Export Control Information /docs/en/supporting-information/P3041PECI.pdf /docs/en/supporting-information/P3041PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N P3041 Family Customer Export Control Information 白皮书 White Paper 4 41 0 English In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. 1580452712610724357770 PSP 317.1 KB None None documents None 1580452712610724357770 /docs/en/white-paper/SPECTREPPCWP.pdf 317053 /docs/en/white-paper/SPECTREPPCWP.pdf SPECTREPPCWP documents N N 2020-01-30 Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf /docs/en/white-paper/SPECTREPPCWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jan 30, 2020 918633085541740938 White Paper Y N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 42 0 English This white paper demonstrates how to best architect software to leverage the DPAA hardware. 1338565191762730130183 PSP 1.1 MB None None documents None 1338565191762730130183 /docs/en/white-paper/QORIQDPAAWP.pdf 1051628 /docs/en/white-paper/QORIQDPAAWP.pdf QORIQDPAAWP documents N N 2016-10-31 QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf /docs/en/white-paper/QORIQDPAAWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jun 1, 2012 918633085541740938 White Paper Y N QorIQ DPAA Primer for Software Architecture 43 2 English This paper discusses the objectives of the trust architecture, how it works, and logistical considerations. 1283981132878727112937 PSP 650.6 KB Registration without Disclaimer None documents Extended 1283981132878727112937 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf 650609 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf QORIQTAWP documents Y N 2016-10-31 An Introduction to the QorIQ Platform's Trust Architecture /webapp/Download?colCode=QORIQTAWP&lang_cd=zh /secured/assets/documents/en/white-paper/QORIQTAWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en May 10, 2011 918633085541740938 White Paper Y N An Introduction to the QorIQ Platform's Trust Architecture 44 0 English CritialBlue&#13;&#10;&#13;&#10;Prism software 1289917463417712987902 PSP 673.1 KB None None documents None 1289917463417712987902 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 673125 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf LTEWHTPPRCRTBLA4 documents N 2016-10-31 Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf White Paper N 918633085541740938 2022-12-07 pdf en Nov 16, 2010 918633085541740938 White Paper N Tuning QorIQ Processor Performance false 0 P3041 downloads zh-Hans true 1 Y PSP 产品简介 1 /docs/en/product-brief/P3041PB.pdf 2016-10-31 1321648686150710474517 PSP 38 Nov 18, 2011 Product Brief This document provides an overview of the P3041 QorIQ<sup>&#174;</sup> communications processor features as well as application use cases. None /docs/en/product-brief/P3041PB.pdf English documents 334333 None 899114358132306053 2023-06-19 N /docs/en/product-brief/P3041PB.pdf P3041 QorIQ Communications Processor Product Brief /docs/en/product-brief/P3041PB.pdf documents 899114358132306053 Product Brief N en None pdf 0 N N P3041 QorIQ Communications Processor Product Brief 334.3 KB P3041PB N 1321648686150710474517 参考手册 5 /secured/assets/documents/en/reference-manual/P3041RM.pdf 2016-10-31 1320688668486717938373 PSP 6 Jul 11, 2016 Reference Manual P3041 can be used for combined control, datapath, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing&#13;&#10;systems. Registration without Disclaimer /secured/assets/documents/en/reference-manual/P3041RM.pdf English documents 17622084 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=P3041RM&lang_cd=zh P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/P3041RM.pdf documents 500633505221135046 Reference Manual N en Extended pdf 4 Y N P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual 17.6 MB P3041RM N 1320688668486717938373 /docs/en/reference-manual/E500MCRM.pdf 2016-10-31 1317141680002726866677 PSP 7 Jul 9, 2015 Reference Manual E500MCRM: The e500mc core is a low-power implementation of the resources for embedded processors defined by the Power ISA &#8482;. The core is a 32-bit implementation and implements 32 32-bit general-purpose registers; however it supports accesses to 36-bit physical addresses None /docs/en/reference-manual/E500MCRM.pdf English documents 5320755 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/E500MCRM.pdf E500MCRM, e500mc Core Reference Manual with Updates /docs/en/reference-manual/E500MCRM.pdf documents 500633505221135046 Reference Manual N en None pdf 3 N N E500MCRM, e500mc Core Reference Manual with Updates 5.3 MB E500MCRM N 1317141680002726866677 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 8 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM&lang_cd=zh EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /secured/assets/documents/en/reference-manual/DPAARM.pdf 2016-10-31 1301610099994679235703 PSP 9 Nov 4, 2011 Reference Manual This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. Registration without Disclaimer /secured/assets/documents/en/reference-manual/DPAARM.pdf English documents 19426366 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=DPAARM&lang_cd=zh QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /secured/assets/documents/en/reference-manual/DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 2 Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual 19.4 MB DPAARM N 1301610099994679235703 /secured/assets/documents/en/reference-manual/P3041SECRM.pdf 2016-10-31 1319838519472711002442 PSP 10 Oct 28, 2011 Reference Manual Registration without Disclaimer /secured/assets/documents/en/reference-manual/P3041SECRM.pdf English documents 6991784 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=P3041SECRM&lang_cd=zh P3041 Security (SEC 4.2) Reference Manual /secured/assets/documents/en/reference-manual/P3041SECRM.pdf documents 500633505221135046 Reference Manual N en Extended pdf 0 Y N P3041 Security (SEC 4.2) Reference Manual 7.0 MB P3041SECRM N 1319838519472711002442 工程设计要点 1 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 2016-10-31 1299186935006725024525 PSP 37 Mar 3, 2011 Technical Notes Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices Registration without Disclaimer /secured/assets/documents/en/engineering-bulletin/EB739.pdf English documents 492591 None 389245547230346745 2022-12-07 Y /webapp/Download?colCode=EB739&lang_cd=zh COM Express Pin Assignments for QorIQ Devices /secured/assets/documents/en/engineering-bulletin/EB739.pdf documents 389245547230346745 Technical Notes N en Extended pdf 0 Y N COM Express Pin Assignments for QorIQ Devices 492.6 KB EB739 N 1299186935006725024525 应用笔记 23 /docs/en/application-note/AN5295.pdf 2016-10-31 1464124094029726989039 PSP 11 May 24, 2016 Application Note AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. None /docs/en/application-note/AN5295.pdf English documents 401764 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5295.pdf AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 401.8 KB AN5295 N 1464124094029726989039 /docs/zh/application-note/AN5260.pdf 2016-10-31 1456317293250700197105zh PSP 12 Feb 24, 2016 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/zh/application-note/AN5260.pdf Chinese documents 1027928 None 645036621402383989 2022-12-07 N /docs/zh/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf documents 645036621402383989 Application Note N zh None Y pdf 0 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 13 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 14 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /docs/en/application-note/AN4403.pdf 2016-10-31 1398358439319724308174 PSP 15 Apr 24, 2014 Application Note AN4403: This document provides recommendations for new designs based on the P3041. None /docs/en/application-note/AN4403.pdf English documents 494196 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4403.pdf AN4403, P3041 QorIQ Integrated Processor Design Checklist - Application Notes /docs/en/application-note/AN4403.pdf documents 645036621402383989 Application Note N en None pdf Rev 0 N N AN4403, P3041 QorIQ Integrated Processor Design Checklist - Application Notes 494.2 KB AN4403 N 1398358439319724308174 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 16 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=zh AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 17 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 18 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=zh AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4375.pdf 2016-10-31 1329517560294722281831 PSP 19 Jun 21, 2012 Application Note This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. None /docs/en/application-note/AN4375.pdf English documents 216552 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4375.pdf QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf documents 645036621402383989 Application Note N en None pdf 1 N N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 216.6 KB AN4375 N 1329517560294722281831 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 20 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 21 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=zh SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN4290.pdf 2016-10-31 1301697264409722558859 PSP 22 Apr 1, 2011 Application Note This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4290.pdf English documents 648695 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4290&lang_cd=zh Configuring the Data Path Acceleration Architecture (DPAA) /secured/assets/documents/en/application-note/AN4290.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Configuring the Data Path Acceleration Architecture (DPAA) 648.7 KB AN4290 N 1301697264409722558859 /docs/en/application-note/AN3423.pdf 2016-10-31 1287581868481730872047 PSP 23 Oct 6, 2010 Application Note None /docs/en/application-note/AN3423.pdf English documents 141965 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3423.pdf Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf documents 645036621402383989 Application Note N en None pdf 0 N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 142.0 KB AN3423 N 1287581868481730872047 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 24 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=zh DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 25 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 26 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 27 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /docs/en/application-note/AN2490.pdf 2016-10-31 1060017730134725666689 PSP 28 Sep 23, 2009 Application Note Application Note None /docs/en/application-note/AN2490.pdf English documents 612895 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2490.pdf MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf documents 645036621402383989 Application Note N en None pdf 1 N MPC603e and e500 Register Model Comparison 612.9 KB AN2490 N 1060017730134725666689 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 29 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869&lang_cd=zh Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3550.pdf 2016-10-31 1208458263255715391554 PSP 30 Oct 22, 2008 Application Note This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. None /docs/en/application-note/AN3550.pdf English documents 505720 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3550.pdf Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf documents 645036621402383989 Application Note N en None pdf 1.0 N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 505.7 KB AN3550 N 1208458263255715391554 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 31 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 32 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 33 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 应用笔记软件 1 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 35 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 手册 2 /docs/en/brochure/PWRARBYNDBITSTA.pdf 2016-10-31 1326753923169722820717 PSP 36 Feb 7, 2012 Brochure None /docs/en/brochure/PWRARBYNDBITSTA.pdf English documents 477805 None 712453003803778552 2022-12-07 /docs/en/brochure/PWRARBYNDBITSTA.pdf Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) /docs/en/brochure/PWRARBYNDBITSTA.pdf documents 712453003803778552 Brochure N en None pdf 0 N Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) 477.8 KB PWRARBYNDBITSTA N 1326753923169722820717 /docs/en/brochure/P2P3P5APPBRF.pdf 2016-10-31 1316699641906701481590 PSP 1 Sep 14, 2012 Brochure 手册 The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. None /docs/en/brochure/P2P3P5APPBRF.pdf English 758908 None Brochure 2022-12-07 N /docs/en/brochure/P2P3P5APPBRF.pdf QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf documents 712453003803778552 Brochure N Y en None t518 pdf 1 N N QorIQ P2040/P2041, P3 and P5 Series - Brochures 758.9 KB P2P3P5APPBRF N 1316699641906701481590 支持信息 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 39 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/P3041PECI.pdf 2016-10-31 1292347734027724236696 PSP 40 Dec 10, 2010 Supporting Information None /docs/en/supporting-information/P3041PECI.pdf English documents 149978 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/P3041PECI.pdf P3041 Family Customer Export Control Information /docs/en/supporting-information/P3041PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N P3041 Family Customer Export Control Information 150.0 KB P3041PECI N 1292347734027724236696 数据手册 1 /secured/assets/documents/en/data-sheet/P3041EC.pdf 2016-10-31 1339783482524703861868 PSP 5 Feb 22, 2013 Data Sheet This document describes the electrical characteristics of the P3041. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P3041EC.pdf English documents 2829137 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=P3041EC&lang_cd=zh P3041 QorIQ Integrated Processor Hardware Specifications /secured/assets/documents/en/data-sheet/P3041EC.pdf documents 980000996212993340 Data Sheet N en Extended pdf 2 Y N P3041 QorIQ Integrated Processor Hardware Specifications 2.8 MB P3041EC N 1339783482524703861868 用户指南 1 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC 2019-12-18 https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y Y 1576719019599707128294 PSP 34 Nov 14, 2019 User Guide None /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC English Y documents Y None 132339537837198660 2022-12-07 N https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Spectre and Meltdown Updates for Power ISA Cores /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC documents 132339537837198660 User Guide N en None Y 1 N N Spectre and Meltdown Updates for Power ISA Cores SPECTRE-MELTDOWN-POWER-ISA-DOC N 1576719019599707128294 白皮书 5 /docs/en/white-paper/SPECTREPPCWP.pdf 2020-01-30 1580452712610724357770 PSP 41 Jan 30, 2020 White Paper In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. None /docs/en/white-paper/SPECTREPPCWP.pdf English documents 317053 None 918633085541740938 2022-12-07 N /docs/en/white-paper/SPECTREPPCWP.pdf Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 317.1 KB SPECTREPPCWP N 1580452712610724357770 /docs/en/white-paper/QORIQDPAAWP.pdf 2016-10-31 1338565191762730130183 PSP 42 Jun 1, 2012 White Paper This white paper demonstrates how to best architect software to leverage the DPAA hardware. None /docs/en/white-paper/QORIQDPAAWP.pdf English documents 1051628 None 918633085541740938 2022-12-07 N /docs/en/white-paper/QORIQDPAAWP.pdf QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N QorIQ DPAA Primer for Software Architecture 1.1 MB QORIQDPAAWP N 1338565191762730130183 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf 2016-10-31 1283981132878727112937 PSP 43 May 10, 2011 White Paper This paper discusses the objectives of the trust architecture, how it works, and logistical considerations. Registration without Disclaimer /secured/assets/documents/en/white-paper/QORIQTAWP.pdf English documents 650609 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=QORIQTAWP&lang_cd=zh An Introduction to the QorIQ Platform's Trust Architecture /secured/assets/documents/en/white-paper/QORIQTAWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 2 Y N An Introduction to the QorIQ Platform's Trust Architecture 650.6 KB QORIQTAWP N 1283981132878727112937 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 2016-10-31 1289917463417712987902 PSP 44 Nov 16, 2010 White Paper CritialBlue&#13;&#10;&#13;&#10;Prism software None /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf English documents 673125 None 918633085541740938 2022-12-07 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf documents 918633085541740938 White Paper N en None pdf 0 N Tuning QorIQ Processor Performance 673.1 KB LTEWHTPPRCRTBLA4 N 1289917463417712987902 /docs/en/white-paper/QORIQSECBOOTWP.pdf 2016-10-31 1317136062337713598350 PSP 4 Jan 25, 2013 White Paper 白皮书 Security continues to be an increasingly important concern in the design of modern systems. Threats against networks and network-connected&#13;&#10;devices are real and growing. With an estimated $40 billion (USD)* of data loss per year, service providers and end-users are becoming painfully&#13;&#10;aware of the consequences of unsecured networks and databases. None /docs/en/white-paper/QORIQSECBOOTWP.pdf English 494394 None White Paper 2023-06-19 N /docs/en/white-paper/QORIQSECBOOTWP.pdf Secure Boot - White Paper /docs/en/white-paper/QORIQSECBOOTWP.pdf documents 918633085541740938 White Paper N Y en None t530 pdf 1 N N Secure Boot - White Paper 494.4 KB QORIQSECBOOTWP N 1317136062337713598350 简介 2 /docs/en/fact-sheet/QP3041FS.pdf 2016-10-31 1276547653279726131905 PSP 2 Apr 21, 2014 Fact Sheet 简介 The QorIQ<sup>&#174;</sup> P3041 processor is an optimized, quad-core device built on Power Architecture&#174; technology. The P3041 processor is designed to offer customers a more power- and cost-efficient solution over the P4 product family. None /docs/en/fact-sheet/QP3041FS.pdf English 376879 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/QP3041FS.pdf QorIQ P3041 - Fact Sheet /docs/en/fact-sheet/QP3041FS.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 3 N N QorIQ P3041 - Fact Sheet 376.9 KB QP3041FS N 1276547653279726131905 /docs/en/fact-sheet/P3041DSFS.pdf 2016-10-31 1316723359847701674311 PSP 3 Sep 22, 2011 Fact Sheet 简介 The P3041DS is a flexible development&#13;&#10;system supporting the quad-core P3041&#13;&#10;device. With its 1.5 GHz P3041 and rich&#13;&#10;input/output (I/O) mix, the board is intended&#13;&#10;for development of P3041 in networking and&#13;&#10;Ethernet-centric applications, such as control&#13;&#10;plane and mixed control plane/data plane&#13;&#10;in switches, routers, base station network&#13;&#10;interface cards, aerospace and defense and&#13;&#10;factory automation. None /docs/en/fact-sheet/P3041DSFS.pdf English 378088 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/P3041DSFS.pdf P3041 Development System /docs/en/fact-sheet/P3041DSFS.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 0 N N P3041 Development System 378.1 KB P3041DSFS N 1316723359847701674311 true Y Products

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