Two-Channel Multipoint Fast-Mode Plus Differential I²C-Bus Buffer with Hot-Swap Logic






System Features

  • New dI2C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
  • 2 channel dI2C (differential I2C-bus) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL drive capability
  • Hot swap (allows insertion or removal of modules or card without disruption to bus data)
  • EN signal (PCA9615 input) controls PCA9615 hot swap sequence
  • Bus idle detect (PCA9615 internal function) waits for a bus idle condition before connection is made
  • Compatible with I2C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to 1 MHz
  • Single-ended I2C-bus on card side up to 540 pF
  • Differential I2C-bus on cable side supporting multi-drop bus
    • Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
    • dI2C output: 1.5 V differential output with nominal terminals
    • Differential line impedance (user defined): 100 Ω nominal suggested
    • Receive input sensitivity: ±200 mV
    • Hysteresis: ±30 mV typical
    • Input impedance: high-impedance (200 kΩ typical)
    • Receive input voltage range: ‑0.5 V to +5.5 V
  • Lock-up free operation
  • Supports arbitration and clock stretching across the dI2C-bus buffers
  • Powered-off and powering-up high-impedance I2C-bus pins
  • Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V tolerant
  • Differential I2C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with 5.5 V tolerant. Best operation is at 5 V.
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Package offering: TSSOP10


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1 设计文件

  • 符号和尺寸

    PCA9615DP-TSSOP10-CAD Symbol and PCB Footprint – BXL File


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