设计文件
快速参考恩智浦
设计文件类型.
2 设计文件
-
印刷电路板与电路图
P3B1602 Evaluation Board Schematics全新
-
设计文件-其他
P3B1602 Evaluation Board Design Files全新
2-bit I3C Bus Buffer with Voltage Level Translation Evaluation Board
- 本页介绍的产品处于样品阶段。此处的产品技术规格和信息如有变更，恕不另行通知。如需了解更多信息和样品供货情况，请联系恩智浦 支持服务或恩智浦当地销售人员。
The P3B1602DP-EVB evaluation board is designed to enable easy testing, validation, and design-in of the P3B1602DP, a 2-bit I3C buffer with integrated auto-direction sensing and bidirectional voltage-level translation.
The standalone evaluation board is populated with series resistors that can be reworked during evaluation. It also supports the selection of different capacitive loads, allowing performance evaluation under various bus-loading conditions.
产品详情
框图
Features
General Features
- Standalone evaluation board for the P3B1602DP 2-bit I3C bus buffer with voltage level translation.
- 30 Ω series resistors included
- Supports capacitive load selection of 0 pF, 50 pF, 100 pF and 150 pF for evaluating performance under different bus loading conditions