设计文件
2 设计文件
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模型
IBIS model for MCM69P/F536C
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模型
Core Model for MCM69F536C Verilog model
The MCM69F536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPCTM, 486, i960TM, and PentiumTM microprocessors.
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2 文件
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2 设计文件
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