202107020I : PCA9635 Datasheet Send at Least 18 Clock Cycles + STOP Condition onto I2C Bus

Updated the following Datasheet sections: 4.0 Ordering Information: Added PCA9635PW/Q900 (AEC-Q100 compliant) 7.5 Power-on reset Added the following paragraph: PCA9635 requires the I2C master device always sends START condition to communicate with PCA9635 after POR (Power-on-Reset) is completed. After the initial START condition than either START or repeated START are acceptable. 8.4 I2C-bus SDA line stuck low recovery mechanism PCA9635 requires I2C master device sends at least 18 clock cycles + STOP condition onto I2C bus if it detects SDA line stuck low by any I2C slave device on the bus vs the normal 9 or more clock cycles due to the register set sequence.

变化的原因

The intend of these updates is to ensure that the customers send at least 18 clock cycles + STOP condition onto I2C bus if it detects SDA line stuck low by any I2C slave device on the bus vs the normal 9 or more clock cycles due to the register set sequence.

预期的影响

数据表的修订: No impact to existing datasheet

受影响的部分