202104035I : PCF8553 Datasheet 9 Clock Pulses after Power-On Requirement

Updated the following Datasheet sections: 7.3 Starting and Resetting the PCF8553 Added "See also application information" comment. 7.3.2 Power-On Reset (POR) Added "The bus interface is initialized" comment. 7.3.3 Hardware Reset: RST pin Removed "The bus interface is initialized" comment. 15.1 Power-on Reset The built-in POR block acts on the rising edge of the VDD supply voltage. Depending on the VDD rising edge in the application the POR may not work properly. Therefore to ensure proper device operation it is required to send nine clock pulses immediately after power-on (see also UM10204).

变化的原因

The intend of these updates is to ensure that the customers send nine clock pulses immediately after power-on (see also UM10204) for the proper device operation; if the POR does not work properly.

预期的影响

数据表的修订: A new datasheet will be issued

受影响的部分