Operational Tests
Operational tab contains a suite of tests designed to verify DDR memory stability after it has been initialized.
Each test contains a set of parameters (like starting address, size of the memory to be tested, pattern, etc.) and the possibility to set a timeout for how long a test should be running. If target is still running and timeout occurs, then a pop-up will appear, and test will end.
- Write-Read-Compare – checks read versus write accesses. Sequentially writes the given pattern into a memory area until it’s fully covered. Then reads back from the same area and compares with the initial pattern. User can set the start address and the size of the area, as well as the pattern to be used. The test fails after the first identified memory mismatch.
- Read-Compare – reads the existing content from flash memory and compares it with the given pattern. User needs to set the start address and the size of the area, as well as the pattern to be used. Alternatively, the pattern can be loaded from file using the "Use input file for pattern" option. The test fails after the first identified memory mismatch.
- Walking Ones - writes a bit pattern that gradually sets bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets set while the others are cleared. For each bit pattern a write-read-compare sequence is performed. The test is repeated for each of the access modes selected using the corresponding size.
- Walking Zeros - writes a bit pattern that gradually clears bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets cleared, while the others are set. For each bit pattern, a write-read-compare sequence is performed. The test is repeated for each of the access modes selected using the corresponding size.
- Stress Test - a collection of tests that verify the performance and
stability of the DDR memory by “stressing” it with different values and access
patterns. There is also a test timer for how long these tests should run. The
suite contains:
- Data is address - This test basically programs the source buffer’s data words with its address (and immediately read-verifies), then copies (memcpy) the source buffer to a destination buffer and verifies the data transferred correctly. For example, if the source address being written to is “0x80000008”, the data value of that address is “0x80000008”. Once the source buffer is completely written, the data is transferred to the destination where it is verified. A basic test to ascertain that simple read/writes work.
- Row hop reading - This test performs single word reads by hopping from one DRAM row to the next, reading the first column in each row and in each bank. Once all the rows are read from the first column, first row from second column follows. The intent is to perform non-sequential reads and to force pre-charge and activate commands before each read access.
- SSN memcpy x32 - This test utilizes a custom written memory copy function that issues load and store pair (LDP, STP) instructions, to test the bursting behavior of the DDR interface. This test uses data patterns to help root out simultaneous switching noise (SSN). This test also breaks up the total DDR density into four “banks” or memory regions, where each bank contains a different SSN data pattern. The test uses various stress patterns such as walking ones and walking zeros, and 0xA’s followed by 0x5’s.
- Byte SSN memcpy x32 - The purpose of this test is to root out any SSN within byte lanes. It accomplishes this by writing byte-wise patterns to one location and the inverse of each byte to the subsequent location. All four bytes values are equal and the test increments the byte pattern as follows (with the inverse value in brackets: 0x00000000 [0xFFFFFFFF]; 0x01010101 [0xFEFEFEFE]; 0x02020202 [0xFDFDFDFD]; … 0xFFFFFFFF [0x00000000]).
- Memcpy random pattern - This test utilizes a custom written memory copy function that issues load and store pair instructions to test the bursting behavior of the DDR interface. The data pattern used is pseudo-random. This test also breaks up the total DDR density into four “banks” or memory regions, where each bank contains a different “seed” for each pseudo-random data pattern.
- IRAM to DDR x32 - The purpose of this test is to root out any SSN and isolates the DDR read and write accesses by using the Internal RAM (IRAM) as an intermediate data storage location. This test moves data from DDR to IRAM and then from IRAM to a different DDR location, then compares DDR location 1 and location 2. This test is similar to the IRAM_to_DDRv1 test (described next), but instead transfers the data 1000 times per test to ensure that the data never changes to root out random glitches. Also, the test uses various data patterns to root out SSN.
- IRAM to DDR x32 v2 - The purpose of this test is to root out any SSN and isolates the DDR read and write accesses by using the IRAM as an intermediate data storage location. This test moves data from DDR to IRAM and then from IRAM to a different DDR location, then compares DDR location 1 and location 2.
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