Timing parameters

DDR Tool uses default timing parameter values, compliant with LPDDR4 JEDEC standard specifications. There are 2 types of parameters:

  • Density dependent parameters (e.g. refresh cycle times, average refresh interval, etc.)
  • Data rate dependent parameters (e.g. read/write latencies)

All the timing parameters are automatically calculated based on JEDEC formulas and the DRAM settings inputted in DDR View (clock frequency, density per channel, number of channels, etc.).

For example, considering a dual rank, dual channel DRAM, with 4Gb density per channel and running at 1600 MHz DDR clock frequency (3200 MT/s data rate) the following values are used:

Table 1. Example of DDR Timing Parameters
Symbol Parameter Value
RL Read-Latency with no DBI 28 nCK
WL Write-Latency of set A 14 nCK
nWR Number of clock cycles used to determine the starting point of an internal Precharge operation after a Write burst with AP 30 nCK
nRTP Number of clock cycles used to determine the starting point of an internal Precharge operation after a Read burst with AP 12 nCK
tREFI Average Refresh Interval (all banks) 3904 us
tREFIpb Average Refresh Interval (per bank) 488 ns
tRFCab Refresh Cycle Time (all banks) 180 ns
tRFCpb Refresh Cycle Time (per bank) 90 ns
tpbR2pbR Per-bank refresh to Per-bank refresh time (different bank) 90 ns
tSR Minimum Self-Refresh time (entry to exit) 15 ns
tXSR Self-Refresh exit to next valid command delay 187.5 ns
tXP Exit Power-Down to next valid command delay 7.5 ns
tRPbp Row precharge time (single bank) 18 ns
tRPab Row precharge time (all banks) 21 ns
tRAS min Minimum time between activate and precharge to the same bank 42 ns