Configuration parameters

Following options are available:

  • DDR type - can be LPDDR4 or DDR3L and is selected according to DDR memory on the board.
  • Clock Cycle Frequency - list of predefined frequencies for DDR. Following table may help in choosing a frequency.
    Table 1. DDR mapping
    Clock Cycle Frequency (MHz) Data Transfer Rate (MT/s)
    800 1600
    1066 2133
    1333 2666
    1516 3032
    1600 3200
  • Oscillator bypass – allows the user to configure the oscillator with custom settings bypassing the default tool's XOSC configuration
  • XOSC clock frequency – Input clock reference
  • DDR_CLK frequency - is the frequency that DDR subsystem should consume. Following table may help to configure correct clock for DDR PLL. For more details please consider microcontroller datasheet.
    Table 2. DDR_CLK
    DDR input clock (MHz) Data Transfer Rate (MT/s)
    400 1600
    533.3 2133
    666.6 2666
    758 3032
    800 3200
  • Density per channel - Amount of Gb per channel. Information can be extracted from memory datasheet. Please see bellow an example of LPDDR4 memory specifications extracted from datasheet. In this example, Density per channel is 8Gb.
    Figure 1. DDR LPDDR4
  • Number of ROW Addresses - Is calculated based on Density per Channel selection. In example figure it's mentioned as R[15:0].
  • Number of chip selects used - Can be extracted from DDR memory datasheet. In example is mentioned as 2 chip selects.
  • Number of channels - Can be extracted from DDR memory datasheet. In example is mentioned as 2 channels.
  • Number of Column addresses - Can be extracted from DDR memory datasheet. In example is mentioned as C[9:0].
  • Number of Banks addresses - Can be extracted from DDR memory datasheet. In example can be extracted from Number of banks - 2^3=8 hence Number of Banks addresses is [2:0].
  • Number of Banks - Is calculated based in Number of Banks addresses. In this example are 8 banks.
  • Total DRAM Density - Calculated based on the previously selected values. In the example is 32Gb (Density per channel * Number of channels * Number of Chip Selects).
  • Bus Width - Is calculated based on Number of Channels: number_of_channels * 16 DQ.
  • Clock Cycle Time - Is time representation of Clock Cycle Frequency selected.
  • DBI – enable read and write data bus inversion
  • PHY ODT Impedance - Select On Die Termination impedance value used by PHY during reads.
  • PHY Drive Strength - Select the driver impedance value used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
  • PHY Vref Quotient - Should be programmed with the Vref level to be used by the PHY during reads. The units of this field are a percentage of VDDQ according to the following equation: PHY Vref = VDDQ * PhyVrefQuotient[6:0] / 128.
  • PHY Vref - Vref value calculated with above formula, based on PHY Vref Quotient value.
  • DRAM ODT Impedance - Select On Die Termination impedance value used by DRAM during writes.
  • DRAM Drive Strength - Select the driver impedance value used by DRAM during reads.
  • CA Vref training - This training is enabled by default and it should provide the best value for CA voltage reference. The user is able to select a desired range number and percentage by disabling this training option.
    Figure 2. CA Vref training
  • Enable Inline ECC - Error Correction Code: mechanism to detect (and even correct) errors in data when reading from and writing to DDR memory. When Inline ECC is enabled, for each byte of data 1 additional bit is reserved for the error checking code. This means that only 7/8 of the total DDR memory will be available.
  • Train 2D - Option to select if training should perform optional (yet highly recommended) 2D stage. 2D training is performed after 1d training to further refine system’s delay and voltage settings and is available only for LPDDR4. Due to I/O construction DDR3 can't have 2D training as its voltage reference is fixed. More details on this feature are available in Diag test training.
  • PHY log level - controls the verbosity of the log messages provided by PHY which may contain additional information during training: MR register values, CA training, etc.
  • Static Refresh Rate [0.25x] - Disable automatic refresh rate and adjust register settings for static refresh rate of 0.25X. Auto Derating Errata is not applicable if this option is enabled.
  • Per Bank Refresh - Enable alternative refresh scheme in which the refresh is executed one memory bank a time, allowing the other banks to be used for read/write accesses. This option is available for LPDDR4 and only if density per channel value does not exceed 4 Gb and static refresh rate is not used.
  • Auto Derating Errata – If the system is hot or cold prior to enabling derating, temperature update flag (TUF) might not be set in MR4 register, causing incorrect refresh period and timing parameters being used (tRCD, tRAS, tRP, tRRD). Software workaround requires reading MR4 during initialization, disabling auto-derating and adjusting timing parameters, if necessary. When this option is enabled, poll_derating_temp_errata method needs to be periodically called from user application, in order to monitor TUF and enable auto-derating logic when possible. In case DDR traffic can be halted, timing parameters can also be restored (see traffic_halted parameter). This option is not applicable if Static Refresh Rate is used.
  • DQ Swapping - due to various possibilities of routing of DDR memory, DQ lines can be swapped. General rules that apply to DQ swapping:
    1. All values must be unique.
    2. It is allowed swapping at bit lane level. For example: 1 and 4 can be mapped inside [7:0] lane but cannot be mapped inside [15:8] lane.
    To mention here that mapping is done from memory perspective, i.e. upper line represents the DDR memory and the lower line represents the MCU.
  • Code format - the code format to be applied for the DDR generated files. Depending on the selection, different memory read/write API and coding style are used. Available options are: U-boot, ATF and MISRA.
  • Save debug messages – Controls whether the generated code will save PHY debug messages at the specified address. Memory dump can be consumed by the tool for decoding the messages received during training.
    Figure 3. Save debug messages

  • Advanced Settings - option to disable the ASIL-B/ASIL-D PMIC watchdog. If the option is enabled, a new field will be displayed in which a DCD binary image must be selected. The image will be used to interact with the PMIC registers.

    Note: Default images are provided at ..\installation_folder\eclipse\mcu_data\processors\ \PlatformSDK..\scripts\ddrv\binaries\pmic_dcd_images\ location. Custom images are supported as long as they meet the DCD tool format.