The clock model consists of interconnected clock elements. The clock signal flows from the clock sources through various clock elements to the clock outputs. The clock element can have specific enable conditions that can stop the signal from being passed to the successor. The clock element can also have specific constraints and limits that are watched by the Clocks Tool. To inspect these details, position the cursor on the element in the clock diagram to display the tooltip.
The following are the clock model elements.
- Clock source – Produces a clock signal of a specified frequency. If
it's an external clock source, it can have one or more related pins. Figure 1. Clock source
- Clocks selector (multiplexer) – Selects one input from multiple inputs and passes
the signal to the output. Figure 2. Clocks selector
- Prescaler – Divides or multiplies the frequency with a selectable or fixed
ratio. Figure 3. Prescaler
- Frequency Locked Loop (FLL) – Multiplies an input frequency with given
factor. Figure 4. Frequency Locked Loop
- Phase Locked Loop (PLL) – Contains pre-divider and thus is able to
divide/multiply with a given value. Figure 5. Phase Locaked Loop
- Clock gate – Stops the propagation of incoming signal.
- Clock output –
Marks the clock signal output that has some name and can be further used by the
peripherals or other parts of the processor. You can put a lock and/or frequency
request. Figure 6. Clock output
- Clock component – Group of clock elements surrounded with a border.
The clock component can have one or more outputs. The clock component usually corresponds
to the processor modules or peripherals. The component output may behave like clock gates,
allowing or preventing the signal flow out of the component. Figure 7. Clock component
- Configuration element – Additional setting of an element. Configuration elements do not have graphical representation in the diagram. They are shown in the setting table for the element or the clock path the element is on.