The Image Signal Processor (ISP) module consists of 8 Image Processing Unit Scalar (IPUS) engines and 4 Image Processing Unit Vector (IPUV) engines.
- IPUS Engine - IPU Scalar Engine
- IPUV Engine - IPU Vector Engine
The Scalar and Vector IPU Engines have the following set of properties:
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- Name - Name of the IPU Engine. The name must be a valid C identifier, must be unique and can't exceed 63 characters.
- Kernel - Name of the kernel. Click ... to change the kernel. Note that the chosen processing kernel must match the Engine Type.
- Engine Index - Engine number. Valid values: 0-7 for IPUS and 0-3 for IPUV.
- Engine Type - Type of the engine: VECTOR or SCALAR.
- Processing Steps Quantity - Number of processing steps.
- Parameters - Advanced parameters. In this field you can configure register
offsets.
- IPUS registers:
Register Description IPUS_HOST_INxCFG This register provides the configuration for the INx input matrix, where INx stands for input matrix: INA, INB or INALPHA. This register holds the configuration for the next line in lower 16-bits and reflects the configuration status of the currently processed line in higher 16-bits. IPUS_HOST_XCFG This register provides the horizontal configuration for the next line to be processed. Horizontal configuration holds the width (XSIZE) of the line and increment step (XSTEP) for the horizontal position core register i.e. XPOS. Difference between the XSIZE and XPOS register is indicated in the REMAIN_PIXELS field of the IPUS_HOST_STATUS registers. Instruction execution is stopped when the value of XPOS register becomes greater than or equal to value held in XSIZE field. IPUS_HOST_OUTCFG This register provides the configuration for the OUT input matrix. This register holds the configuration for the next line in lower 16-bits and reflects the configuration status of the currently processed line in higher 16-bits. IPUS_S_CHn_CFG_INx IPUS_S_CH0_CFG_INx - Stream Line 0 Configuration Register provides mechanism to configure the channel parameters corresponding to the first row vector (INx0-INx2) in 3x3 INx matrix configuration or the only row vector (INx0-INx8) in 1x9 INx matrix configuration, where INx stands for input matrix: INA, INB or INALPHA. IPUS_S_CH1_CFG_INx - Stream Line 1 Configuration Register provides mechanism to configure the channel parameters corresponding to the second row vector (INx3-INx5) in 3x3 INx matrix configuration. In 1x9 INx matrix configuration the contents of this register is not used as only one stream is enabled, where INx stands for input matrix: INA, INB or INALPHA. IPUS_S_CH2_CFG_INx - Stream Line 2 Configuration Register provides mechainsm to configure the channel parameters corresponding to the third row vector (INx6-INx8) in 3x3 INx matrix configuration. In 1x9 matrix configuration the contents of this register are ignored as only one stream is enabled, where INx stands for input matrix: INA, INB or INALPHA. IPUS_S_CHn_CFG_OUT This register provides the configuration for the stream channel corresponding to the OUTn element of the OUT matrix, where n stands for the channel: 0, 1, 2 or 3. - IPUV registers:
Register Description IPUV_HOST_INCFG This register provides the configuration for the IN input matrix. This register holds the configuration for the next line in lower 16-bits and reflects the configuration status of the currently processed line in higher 16-bits. IPUV_HOST_XCFG This register provides the horizontal configuration for the next line to be processed. Horizontal configuration holds the width (XSIZE) of the line and increment step (XSTEP) for the horizontal position counter i.e. XPOS counter. Difference between the XSIZE and XPOS counter is indicated in the REMAIN_PIXELS field of the IPUV_HOST_STATUS registers. IPUV_HOST_OUTCFG This register provides the configuration for the OUT matrix. This register holds the configuration for the next line in lower 16-bits and reflects the configuration status of the currently processed line in higher 16-bits. IPUV_S_CHn_CFG_IN IPUV_S_CH0_CFG_IN - Stream Line 0 Configuration Register provides mechanism to configure the channel parameters corresponding to the first row vector in 5x8 IN matrix configuration IPUV_S_CH1_CFG_IN - Stream Line 1 Configuration Register provides mechanism to configure the channel parameters corresponding to the second row vector in 5x8 IN matrix configuration IPUV_S_CH2_CFG_IN - Stream Line 2 Configuration Register provides mechanism to configure the channel parameters corresponding to the third row vector in 5x8 IN matrix configuration IPUV_S_CH3_CFG_IN - Stream Line 3 Configuration Register provides mechanism to configure the channel parameters corresponding to the fourth row vector in 5x8 IN matrix configuration IPUV_S_CH4_CFG_IN - Stream Line 4 Configuration Register provides mechanism to configure the channel parameters corresponding to the fifth row vector in 5x8 IN matrix configuration IPUV_S_CHn_CFG_OUT IPUV_S_CH0_CFG_OUT - This register provides the configuration for the stream channel corresponding to the OUT0-OUT3 vector of the OUT matrix. IPUV_S_CH1_CFG_OUT - This register provides the configuration for the stream channel corresponding to the OUT4-OUT7 vector of the OUT matrix. IPUV_S_CH2_CFG_OUT - This register provides the configuration for the stream channel corresponding to the OUT8-OUT11 vector of the OUT matrix.
Note: For more details refer to S32V234 Reference Manual, which can be found in <install_dir>\S32DS\help\resources\hardware. - IPUS registers: