There are two caches available in a Pioneer 3 MCU. The Code Cache, which is associated with the Processor Code (PC) Bus and the System Cache, associated the Processor System (PS) bus. One important aspect here is that both are unified caches, meaning that both are capable of storing instructions and data as well. However, as the bus names imply, the typical operations issue code accesses on the PC bus and the data accesses on the PS bus. The buses are partitioned as follows:
- The memory accesses to the addresses from 0x0 to 0x1FFFFFFF use the PC bus.
- The memory accesses to the addresses from 0x20000000 to 0xFFFFFFFF use the PS bus.
The figure below describes the Kinetis P3 local memory controller.
In terms of structure, the Code Cache and the System Cache are identical. Each of them has 8KB, they are 2-way set associative and have four word lines (16 bytes).
Whenever a cache address is targeted to be processed by the cache module, its address generates the Tag and the Cache Line in a way, that the upper 20 bits represent the Tag and the next 8 bytes represent the Line. The bits 3-2 determine the word within a line and bits 1-0 determine the byte within a word.
Whenever a cache-miss occurs, one line data consisting in 16 bytes will be stored into the cache in the cache data array at the line number index at one available way. In addition the line tag will be stored into the cache tag array at the line number index.
Each cache line has the following properties:
- Valid - the cache line contains valid data that can be used instead of the corresponding data from the memory
- Modified (Dirty) - the cache line is modified by the core, but its content is not saved back to the corresponding memory yet.
The Kinetis local memory controller supports three modes of operation: