The non-cacheable accesses bypass the cache and access the output bus.
The Kinetis memory map contains multiple regions as shown in the following table. Each region has one or more available cache modes.
The Kinetis architecture supports the following cache operations:
- Read - The cache data and tag are accessible for reading.
- Write - The user is able to modify the cache data using the Local Memory Controller support.
- Invalidate - Unconditionally clear, valid and modify bits of a cache entry.
- Push (or Synchronize) - Writes a cache entry in the memory if it is valid and modified, then clear the modify bit. If entry not valid or not modified, leave as is.
- Clear (or Flush) - Push a cache entry if it is valid and modified, then clear the valid and modify bits. If the entry is not valid or not modified, clear the valid bit.
The scope of Invalidate, Push and Clear commands may be a particular cache line or an entire cache way.