The write-back operation inculdes:
- A write-back read miss on the input bus causes a line read on the output bus of a 16-byte-aligned memory address containing the desired address. This miss data is loaded into the cache and marked as valid and not modified.
- A write-back read hit to a valid cache location returns data from the cache with no output bus access.
- A write-back write miss brings the corresponding line into the cache (allocate on write miss policy). If the line to be brought into the cache, replaces another dirty line, the latter is saved back to the memory before reading the new line. In this case, a line read on the output bus of a 16 byte aligned memory address containing the desired write address is performed.