Use this panel to specify processor behavior. You can specify the file paths and define macros.
The following table lists and defines each option of the Processor panel.
| Option | Description |
|---|---|
| Struct Alignment | The Struct Alignment drop-down list has the default selection PowerPC. To conform with the PowerPC EABI and interoperate with third-party object code, this setting should remain PowerPC. Other settings may lead to reduced performance or alignment violation exceptions. If you choose another setting for Struct Alignment, your code may not work correctly. The options available are as follows:
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| Function Alignment | If your board has hardware capable of fetching multiple instructions at a time, you may achieve slightly better performance by aligning functions to the width of the fetch. Use the Function Alignment drop-down list to select alignments from 4 bytes (the default) to 128 bytes. These selections corresponds to #pragma function_align. |
| Relax HW IEEE | The Relax HW IEEE checkbox is available only if you select Hardware from the Floating Point drop-down list. Check the The Relax HW IEEE checkbox to have the compiler generate faster code by ignoring certain strict requirements of the IEEE floating-point standard. These requirements are controlled by the options:
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| Use Fused Mult-Add/Sub | Check to generate PowerPC Fused Multi-Add/Sub instructions, which result in smaller and faster floating-point code. This may generate unexpected results because of the greater precision of the intermediate values. The generated results are slightly more accurate than those specified by IEEE because of an extra rounding bit between the multiply and the add/subtract. |
| Generate FSEL Instructions | Check to generate the faster executing FSEL instruction. The FSEL option allows the compiler to optimize the pattern x = (condition ? y : z), where x and y are floating-point values. FSEL is not accurate for denormalized numbers and may have issues related to unordered compares. |
| Assume Ordered Compares | Check to allow the compiler to ignore issues with unordered numbers, such as NAN, while comparing floating-point values. In strict IEEE mode, any comparison against NAN, except not-equal-to, returns false. This optimization ignores this provision, thus allowing the following conversion: if (a <= b)to if (b > a) |
| Vector Support | Several processors support vector instructions. If you want to allow vector instructions for your processor, select a vector type that your processor supports from the Vector Support drop-down list. If you select the Altivec option from the Vector Support drop-down list, additional options appear. The options available are as follows:
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| Generate VRSAVE Instructions | Check the Generate VRSAVE Instructions checkbox only when developing for a real-time operating system that supports AltiVec. Checking the Generate VRSAVE Instructions checkbox tells the CodeWarrior software to generate instructions to save and restore these vector-register-related values. The VRSAVE register indicates to the operating system which vector registers to save and reload when a context switch happens. The bits of the VRSAVE register that correspond to the number of each affected vector register are set to 1. When a function call happens, the value of the VRSAVE register is saved as a part of the stack frame called the vrsave word. In addition, the function saves the values of any non-volatile vector registers in the stack frame as well, in an area called the vector register save area, before changing the values in any of those registers. |
| AltiVec Structure Moves | Check if you want the CodeWarrior software to use Altivec instructions when the compiler copies a structure. |
| Make Strings ReadOnly | Check to store string constants in the read-only .rodata section. Clear to store string constants in the ELF-file data section. The Make Strings Read Only checkbox corresponds to #pragma readonly_strings. |
| Merges String Constants | Check to have the compiler pool strings together from a given file. Clear to let the compiler treat each string as an individual string. The linker can deadstrip unused individual. |
| Pool Data | Check to instruct the compiler to organize some of the data in the large data sections of .data, .bss, and .rodata so that the program can access it more quickly. This option only affects data that is actually defined in the current source file; it does not affect external declarations or any small data. The linker is normally aggressive in stripping unused data and functions from the C and C++ files in your project. However, the linker cannot strip any large data that has been pooled. If your program uses tentative data, you get a warning that you need to force the tentative data into the common section. |
| Use Common Section | Check to have the compiler place global uninitialized data in the common section. This section is similar to a FORTRAN Common Block. If the linker finds two or more variables with the same name and at least one of them is in a common section, those variables share the same storage address. If this checkbox is cleared, two variables with the same name generate a link error. The compiler never places small data, pooled data, or variables declared static in the common section. |
| Use LMW _STMW | Check to have the compiler to use LMW/STMW instructions in the prologue and epilogue of a function when appropriate to store and restore volatile registers. |
| Inlined Assembler is Volatile | Check to have the compiler treat all asm blocks (including inline asm blocks) as if the volatile keyword was present. This prevents the asm block from being optimized. You can use the .nonvolatile directive to selectively enable optimization on asm blocks, as required. |
| Instruction Scheduling | Check to optimize the scheduling of instructions for the specific processor you are targeting (determined by which processor is selected in the Processor drop-down list.) Enabling the Instruction Scheduling checkbox can make source-level debugging more difficult because the source code may not correspond to the execution order of the underlying instructions. It is sometimes helpful to clear this checkbox when debugging, and then check it again once you have finished the bulk of your debugging. |
| Peephole Optimization | Check to have the compiler perform peephole optimizations. Peephole optimizations are small local optimizations that can reduce several instructions into one target instruction, eliminate some compare instructions, and improve branch sequences. This checkbox corresponds to #pragma peephole. |
| Profiler Information | Check to generate special object code during runtime to collect information for a code profiler. This checkbox corresponds to #pragma profile. |
| Generate ISEL Instructions (e500/Zen) | Check to have the compiler to emit ISEL instructions. This instruction can improve performance by reducing conditional branching. |
| Translate PPC Asm to VLE Asm (Zen) | Check to have the compiler to translate the classic PPC inline assembly instructions to the VLE inline assembler for the Zen processor. |