Programmable Delay Block Module

In Full Chip Simulation (FCS) Mode, this module lets you simulate all the functionality of the Programmable Delay Block (PDB) module. This module's primary function is to provide a controllable delay from FTM SYNC output to the sample trigger input of PGA or ADC, or a controllable window synchronized with PWM pulses for ACMP to compare the analog signals in a defined window. PDB can alternately generate PWM pulses that are synchronized to FTM, CMPR output, and RTC.