Data MATT page

Use the Data MATT page to define and display data memory-space mappings (virtual-to physical address mappings) for the StarCore DSP . The MMU configurator generates the appropriate descriptors for the data memory-address translation table (MATT).

Each memory-space mapping has a corresponding entry in the list on the left-hand side of the Data MATT page. Each entry shows an abbreviated expression which summarizes the settings on the right-hand side of the page. A plus sign to the left of an entry indicates an enabled mapping, and a minus sign indicates a disabled mapping.

To change an entry, select it from the left-hand side of the page, then use the Address, Size, and Properties settings to specify options that the MMU configurator verifies as a group. Click the Change button to assign the specified options to the selected entry. To cancel your changes, select another entry from the left-hand side of the page, without clicking the Change button.

The following figure shows the Data MATT page.

Figure 1. MMU Configuration File Editor - Data MATT page

MMU Configuration File Editor-Data MATT Page

The following table explains each option on the Data MATT page

Table 1. Data MATT page settings
Option	Explanation
Virtual	Enter the virtual base address of the data segment. This option corresponds to the Data Segment Virtual Base Address and Size (DSVBAS) bits of the Data Segment Descriptor Registers A (M_DSDAx) that configure the virtual base address.
Physical	Enter the most-significant part of the physical address to use for translation. The value that you specify determines the size of the most- significant part. This option corresponds to the Data Segment Physical Base Address (DSPBA) bits of the Data Segment Descriptor Registers B (M_DSDBx).
Size	Specify the PMATT Units number in Number box. Select the PMATT Units type from the pop-up menu: B, KB, MB, GB
Permissions	Specify whether to share the data segment: shared and non-shared This option corresponds to the Supervisor/Shared Virtual Data Memory (SSVDM) bit of the Data Segment Descriptor Registers A (M_DSDAx).
Burst	Specify the number of transactions (beats) on the bus that the bus controller cannot interrupt. This burst size applies in the region to a cacheable segment. This option corresponds to the Data Burst Size (DBS) bits of the Data Segment Descriptor Registers B (M_DSDBx).
L2 Cache Policy	Determines the cache policy for the L2 cache for accesses from the core through L1 Data Cache: Cacheable write through, Cacheable write-back, Non-cacheable, and Adaptive write.
DAPU	Specify whether to allow user-level read (r-), write (-w), both (rw), or neither(--) types of data access. This option corresponds to the Data Access Permission in User Level (DAPU) bits of the Data Segment Descriptor Registers A (M_DSDAx).
DAPS	Specify whether to allow supervisor-level read (r-), write (-w), both (rw), or neither (--) types of data access. This option corresponds to the Data Access Permission in Supervisor Level (DAPS) bits of the Data Segment Descriptor Registers A (M_DSDAx).
Write Policy	Specify the policy to use for data writes and cache: Cacheable write through-Writes are buffered in the write queue (WRQ) and goes both to the cache and to the higher-level memory. The write-through is a non-write allocate, and a cacheable write-through access is not updated in the cache unless there is a hit. Cacheable write back-writes are buffered in the write queue (WRQ) and goes through the DCache and the write back buffer (WBB). The information is written to the VBR in the cache only. The modified cache VBR is written to higher-level memory only when it is replaced. The resulting WBB is combined with a write-allocate write-miss policy in which the required VBR is loaded to cache when a write-miss occurs. Non Cacheable write through-writes are buffered in the WRQ and goes through the write through buffer (WTB) to the higher-level memory Non-cacheable write-through destructive area-writes are buffered in the WRQ and goes through the write through buffer (WTB) to the higher-level memory. Speculative read accesses are blocked in the platform level and does not goes to a higher level memory.
Prefetch Line	Selected - Enables the fetch unit's data-line prefetch to a segment cacheable in data cache. Deselected - Disables the fetch unit's data-line prefetch to a segment cacheable in data cache. This checkbox corresponds to Data Pre-fetch Line Enable (DPFE) bit of the Data Segment Descriptor Registers B (M_DSDBx).
Entry Enabled	Selected - The MMU enables this mapping entry. Deselected - The MMU disables this mapping entry.

Figure 2. MMU Configuration File Editor - Data MATT Table page

MMU Configuration File Editor-Data MATT Table Page

The DMATT Table page ( Figure 2) shows an alternate, tabular rendering of the settings that you specify on the Data MATT page. Use this page to view the configuration of all Data MATT mappings. The MMU configurator uses the settings that you specify on the Data MATT page to generate the column headers of this page. The table data shows the validated records for each Data MATT entry. You can resize the table columns to hide columns or view the larger data fields. A plus sign ( + ) in a table cell represents a selected checkbox in the associated Data MATT configuration page.

Note: The DMATT Table page shows the summary of the settings that you specify on the Data MATT page in the tabular format. To changes these settings, use the Data MATT page.