The DSP56800E processor has a dual Harvard architecture with separate CODE (P: memory) and DATA (X: memory) memory spaces. The following table shows the sizes and ranges of these spaces, as well as the range of character data within X memory, for both the small and large memory models. (You may need to use the ELF Linker and Command Language or M56800E Linker settings panel to specify how the project-defined sections map to real memory.)
| Section | Small Model | Large Model | ||
|---|---|---|---|---|
| Size | Range ((Word Address)) | Size | Range ((Word Address)) | |
| CODE (P: memory) | 128 KB | 0 - 0xFFFF | 1 MB | 0 - 0x7FFFF |
| DATA (X: memory) | 128 KB | 0 - 0xFFFF | 32 MB | 0 - 0xFFFFFF |
| DATA (X: memory) character data | 64 KB | 0 - 0x7FFF | 16 MB | 0 - 0x7FFFFF |
A peculiarity of the DSP56800E architecture is byte addresses for character (1-byte) data, but word addresses for data of all other types. To calculate a byte address, multiply the word address by 2. An address cannot exceed the maximum physical address, so placing character data in the upper half of memory makes the data unaddressable. (Address registers have a fixed width.)
For example, in the small memory model (maximum data address: 64 KB), placing character data at 0x8001 requires an access address of 0x10002. But this access address does not fit into 16-bit storage, as the small data memory model requires. Under your control, the compiler increases flexibility by placing all character data into specially-named sections as described in DSC Compiler > Processor. You can locate these sections in the lower half of the memory map, making sure that the data can be addressed.