This transformation replaces several accesses to adjacent stack locations with a post-increment/-decrement addressing mode by using an available address register.
For DSP56800E, this transformation may bring performance gain both in execution speed and code size. Speed is improved as instructions using post-increment access usually take only one cycle as opposed to instructions with immediate offsets that can take 2 or 3 cycles. Code size is reduced when large immediates are present.
An example of stack sequence optimization where the following low-level intermediate piece of code:
move.w X:(SP-2),A move.w X:(SP-1),Y1 move.w X:(SP-2),A move.w X:(SP-3),B add.w X:(SP-4),B
will become:
adda #-2,SP,R0 move.w X:(R0)+,A move.w X:(R0)-,Y1 move.w X:(R0)-,A move.w X:(R0)+,B add.w X:(R0),B
which brings an improvement of 3 cycles (2+2+2+2+3 as opposed to 2+1+1+1+1+2).
In the example above, the transformation actually increases the code size, and that is why it will not be performed on this example when -Os optimization is required.
Note that this transformation makes use of both post increment and post decrement update modes, and it can also exploit all instructions accessing the stack, not only loads and stores.
Transformation is controlled by the -[no]stackseq command line switch, and it is enabled by default for an optimization level higher than one. Also, #pragma stackseq on/off may be used to control the transformation.