Version specific information for RS08

The ROM and RAM ranges depend on the target processor. The RESERVED_RAM size for pseudo registers storage is by default 5 bytes.

Component implementation details:

Interrupts: Some of the RS08 derivatives do not support interrupts so the components on these processors are limited and some are not available. The following components are not available on the RS08 derivatives without interrupt support because they depend on interrupt(s):
ExtInt,TimerInt,FreeCntr8,FreeCntr16,FreeCntr32,RTIshared, InterruptVector,TimeDate

Derivatives of the RS08 family with processor core version 2 support a single global interrupt vector. The interrupt doesn't support a vector table lookup mechanism as used on the HC(S)08 devices. It is the responsibility of a routine servicing the global interrupt to poll the system interrupt pending registers (SIPx) to determine if an interrupt is pending. To support the single global interrupt vector Processor Expert defines a set of emulated interrupt vectors for each HW module, which duplicates interrupt vectors of the HCS08 family. When an emulated interrupt vector is used by a component a call to the appropriate interrupt service routine is added to the global interrupt service routine. The global interrupt vector routine performs check of the SIPx registers to determine if an interrupt is pending. The order in which the SIPx registers are polled is affected by priority of the emulated interrupts. For priority settings, see Processor Expert priority system topic for details.
Processor:
- Speed Mode selection (processor methods SetHighSpeed, SetLowSpeed, SetSlowSpeed ): if processor clock-dependent components are used then signals generated from such internal peripherals may be corrupted at the moment of the speed mode selection (if function of clocked devices is enabled). Handling of such a situation may be done using events BeforeNewSpeed and AfterNewSpeed.
PPG: The PPG components always allocate whole timer. Although it is possible to share the selected timer between 2 PPG components, it would be impossible to set the PPG period for these two components separately.
PWM: In contrast to the PPG components, it is possible for PWM components to share the selected timer, since they do not have the SetPeriod method.
WatchDog: When the Watchdog component is added to the project, it is automatically enabled. The enabling code is placed in the processor initialization code.
Note: Watchdog is enabled by a write to the configuration register. This register can be written only once after processor reset. Since the register also contains other bits, which are written during the processor initialization, the watchdog must be enabled when processor is initialized. The property "CPU clock/speed selection" has no effect because the COP timer clock source is CGMXCLK.
AsynchroSerial: Timing setting 'values from list' enables to select various values denoted by changes of the prescaler most tightly coupled with UART.
SynchroMaster: If a mode fault occurs, the component is disabled at the beginning of the RecvChar method.
SynchroSlave: When Clock edge property = "falling edge", Shift clock idle polarity property = "Low" or Clock edge property = "rising edge" and Shift clock idle polarity property = "High", the SS pin of the slave SPI module must be set to logic 1 between bytes. The falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be loaded with the desired transmit data before the falling edge of SS.
BitIO, BitsIO, ByteIO, Byte2IO, Byte3IO, Byte4IO:
The GetVal and GetDir methods are always implemented as macros. Optimization for property (BitIO, BitsIO) does not influence the generated code.
ADC: Clock input of A/D clock generator cannot be changed in runtime.
A conversion time in the Conversion time dialog is calculated for the worst case.
KBI: Only one KBI component can be used to handle one peripheral in PE project.
For details on sharing and usage of the high-level timer components, see RS08 timers usage and sharing topic for details.