On these RS08 derivatives, the interrupts are handled through single interrupt vector. The priority of each individual emulated interrupt is determined by order in which the SIPx registers are polled in the sofware handler. The priority can be in the range 0 ..number_of_interrupts-1 (for example 0 .. 15). The lower is the number the higher is the priority. The platform independent interrupt priority values in Processor Expert described above are mapped to these values.
The default priority depends on the position of an associated bit in a SIPx register. The interrupt priority can be changed to any value within the allowed range. Interrupts with lower priority number (higher priority of execution) are polled first. If two interrupts have assigned the same priority number then the order in which they are polled depends on the default priority. For more details on interrupts on RS08, refer to the Version specific information for RS08 topic.