JTAG/COP connector information

The CodeWarrior Ethernet TAP JTAG/COP probe has a 16-pin connector which automatically supports target system signal levels from 1.8V to 3.3V.

The following figure shows the pin assignments of the probe JTAG/COP connector.

Figure 1. Ethernet TAP probe for JTAG/COP connector pin assignments

The following table lists JTAG/COP signal names, direction, pin numbers, descriptions, and drive capabilities for the probe JTAG/COP connector.

Table 1. Ethernet TAP probe for JTAG/COP signal directions
JTAG/COP pin	Signal mnemonic	Signal direction	Description
1	TDO	From target system	17pF load
2	QACK	From Ethernet TAP probe connector	100Ohm pull-down
3	TDI	From Ethernet TAP probe connector	50mA driver
4	TRST	From Ethernet TAP probe connector	50mA driver
5	HALTED	Bi-directional	Open-drain, 100Ohm to ground when asserted by Ethernet TAP probe, 22pF load when not asserted¹
6	TGT PWR	From target system	2MOhm pull-down, plus 0.01uF load
7	TCK	From Ethernet TAP probe connector	50mA driver
8	CKSI	From Ethernet TAP probe connector	50mA driver
9	TMS	From Ethernet TAP probe connector	50mA driver
10	No Connect	- n/a -
11	SRST	Bi-directional	Open-drain. 100Ohm to ground when asserted by Ethernet TAP probe, 22pF load when not asserted¹
12	No Connect	- n/a -
13	HRST	Bi-directional	Open-drain. 100Ohm to ground when asserted by Ethernet TAP probe, 22pF load when not asserted¹
14	No Connect	- n/a -
15	CKSO	From target system	17pF load¹
16	GND	- n/a -

The following table provides a general description of each JTAG/COP signal and the operational requirements.

Note: All JTAG/COP signals must meet accepted standards for JTAG/COP signal design. To ensure proper and stable operation between the Ethernet TAP probe and the target system, the JTAG/COP signals must meet the requirements listed in table below.

Table 2. Ethernet TAP probe for JTAG/COP signal recommendations and requirements
JTAG/COPpin	Signal mnemonic	Requirement
1	TDO	Must be wired to the target system processor. TDO is an output from the target system processor and an input to the Ethernet TAP probe. The TDO trace run should be kept short and maintain a "two-signal-width" spacing from any other parallel dynamic signal trace. TDO should have a series termination resistor located near the target system processor.
2	QACK	May be wired to the target system processor. QACK is an input to most PowerPC processors and must remain low while the Ethernet TAP probe is connected to the target system. The Ethernet TAP probe connects this signal internally to the JTAG/COP GND pin (16) through a 100Ohm resistor.
3	TDI	Must be wired to the target system processor. The Ethernet TAP probe drives the TDI output with up to 50mA. The TDI trace should be kept short and maintain a "two-signal-width" spacing from any other parallel dynamic signal trace. TDI should have an RC termination option at the processor.
4	TRST	Must be wired to the target system processor. The Ethernet TAP probe drives the TRST output with up to 50mA. To gain control of the processor, the Ethernet TAP probe negates TRST approximately 250 milliseconds before negation of HRST. This allows the Ethernet TAP probe to issue COP commands through the JTAG/COP interface and gain control of the processor upon negation of HRST. The TRST trace run should be kept short and maintain a "two-signal-width" spacing from any other parallel dynamic signal trace.
5	HALTED	Need not be wired to the target system. The Ethernet TAP probe does not currently use this signal.
6	TGT PWR	Must be wired to the target system. The Ethernet TAP probe uses this signal to determine if power is applied to the target system. This signal is also used as a voltage reference for the signals driven by the Ethernet TAP probe (CKSI, TRST, TCK, TMS, TDI). TGT PWR (pin 6) should be connected to the target system Vcc through a 1KOhm pull-up.
7	TCK	Must be wired to the target system processor. The Ethernet TAP probe drives the TCK output with up to 50mA. The TCK trace run should be kept as short as possible and maintain a "two-signal-width" spacing from any other parallel dynamic signal trace.
8	CKSI	Need not be wired to the target system.The Ethernet TAP probe does not currently use this signal.
9	TMS	Must be wired to the target system processor. The Ethernet TAP probe drives the TMS output with up to 50mA. TMS should be kept as short as possible and maintain a "two-signal-width" spacing from any other parallel dynamic signal trace. TMS should have a termination option at the processor.
10	No Connect	Not required for emulation
11	SRST	May be wired to the target system processor. During reset, the Ethernet TAP probe drives SRST to ground through a 100Ohm resistor.
12	No Connect	Not required for emulation
13	HRST	Must be wired to the target system processor. During reset, the Ethernet TAP probe drives HRST to ground through a 100Ohm resistor.
14	No Connect	Not required for emulation
15	CKSO	Should be wired to the target system processor. The Ethernet TAP probe senses CKSO to determine if the processor halted execution in a checkstop state.
16	GND	Must be wired to the target system. GND is connected directly to the ground inside the Ethernet TAP probe.

Notes specific to MPC8240, MPC8241, and MPC8245

CKSO is not available on the MPC8240, MPC8241, or MPC8245 processors.

SRST can be deselected in favor of the SDMA12 signal used for Extended Addressing (except on the MPC8240 processor).

QACK is an output signal only, so it need not be connected to the COP header.

The Ethernet TAP probe fully supports the MPC8240, MPC8241, and MPC8245 processors despite the absence of the signals mentioned above.

Signal width example

Signal line 'A' is 0.005 mil. An adjacent dynamic signal line 'B' should maintain a "two-signal-widths" distance from signal line 'A'. So that from the center of line 'A' to the center of line 'B', there should be 0.0025 + 0.005 + 0.005 + 0.0025 = 0.015mil.

Target system bias should maintain "one-signal-width" spacing from the signal.