DPI connector information

The CodeWarrior Ethernet TAP DPI probe has a 10-pin connector which automatically supports target system signal levels from 1.8V to 3.3V.

The following figure shows the pin assignments of the probe DPI connector.

Figure 1. Ethernet TAP probe for DPI connector pin assignments

The following table lists DPI signal names, direction, pin numbers, descriptions, and drive capabilities for the probe DPI connector.

Table 1. Ethernet TAP probe for DPI signal directions
DPI pin	Signal mnemonic	Signal direction	Description
1	VLSO/FRZ	From target system	17pF load
2	SRST	Bi-directional	Open-drain. 100Ohm to ground when asserted by Ethernet TAP probe, 22pF load when not asserted
3	GND	- n/a -
4	DSCK	From Ethernet TAP probe connector	50mA driver
5	GND	- n/a -
6	VFLS1/FRZ	From target system	22pF load
7	HRST	Bi-directional	Open-drain. 100Ohm to ground when asserted by Ethernet TAP probe, 22pF load when not asserted¹
8	DSDI	From Ethernet TAP probe connector	50mA driver
9	VDD	From target system	2MOhm pull-down, plus 0.01uF load
10	DSDO	From target system	17pF load

The table below provides a general description of each DPI signal and operational requirements.

Note: All DPI signals must meet accepted standards for DPI signal design. To ensure proper and stable operation between the Ethernet TAP probe and the target system, the DPI signals must meet the requirements listed in the following table.

Table 2. Ethernet TAP probe for DPI signal recommendations and requirements
DPI pin	Signal mnemonic	Requirement
1	VLSO/FRZ	VFLS0/FRZ is not needed for emulation.
2	SRST	Must be wired to the target system. During reset, the Ethernet TAP probe drives SRST to ground through a 100Ohm resistor.
3	GND	Must be wired to the target system. GND is connected directly to the ground inside the Ethernet TAP probe.
4	DSCK	Must be wired to the target system processor. It is driven by the Ethernet TAP probe as an output with up to 50mA. This signal is the clock for the DPI interface. It is good design practice to keep the trace length short and isolate the trace from other signals. If the trace must be long, then termination may be needed.
5	GND	Must be wired to the target system. GND is connected directly to the ground inside the Ethernet TAP probe.
6	VFLS1/FRZ	VFLS1/FRZ is not needed for emulation.
7	HRST	Must be wired to the target system. During reset, the Ethernet TAP probe drives HRST to ground through a 100Ohm resistor.
8	DSDI	Must be wired to the target system processor. The Ethernet TAP probe drives the TDI output with up to 50 mA.
9	VDD	Must be wired to the target system. The Ethernet TAP probe uses this signal to determine if power is applied to the target system. This signal is also used as a voltage reference for the signals driven by the Ethernet TAP probe (SRST, SDCK, HRST, DSDI).
10	DSDO	Must be wired to the target system processor. DSDO is an output from the target system processor and an input to the Ethernet TAP probe. It is good design practice to keep the trace length short and isolate the trace from the other signals.