Breakpoints in Exception/Interrupt Handlers

Care must be taken when setting breakpoints in exception handler code. A typical exception consists of a preamble that saves processor context, the actual exception handler, and then a postamble that restores processor context. You can use software breakpoints in the actual exception handler code, but not in the preamble or postamble where the processor context is changing.

Note: For Embedded Power Architecture processors, placing the CPU into debug mode is just another interrupt. For example: your code is in an interrupt epilogue and has just placed the return address into SRR0 when a breakpoint occurs. The breakpoint causes the IP for the address of the breakpoint to be written to SRR0, destroying your original return address. Stepping through code which accesses SRR0 and SRR1 exhibits the same problem.

To avoid this problem, always set your breakpoints before or after code which accesses SRR0 and SRR1, and never step through such code. For example, you can set your breakpoint anywhere after the interrupt prologue, but before the epilogue.

Instructions that involve the SRR0 and SRR1 registers are "MTSPR SRR0/1,Rx" "MFSPR Rx,SRR0/1," and "RFI."