Configure Kinetis Target

The Kinetis target has different cores and trace modules. For example, Kinetis K series has Cortex M4 core and Kinetis L series has Cortex M0+ core.

To configure the launch configuration for the Kinetis Cortex M4 core:

In the CodeWarrior Projects view, right-click the project and select Debug As > Debug Configurations from the context menu.
The Debug Configurations dialog box appears.
In the Debug Configurations dialog box, expand the CodeWarrior Download configuration in the tree structure on the left, and select the launch configuration corresponding to the project you are using. For example, select TraceProject_RAM_PnE U-MultiLink.
On the Main tab page, verify that name of the project, for example, TraceProject is displayed in the Project field. If it does not appear, click Browse and locate the project.
If the application is not displayed in the Application field, click Search Project to select the application image.
Figure 1. Debug Configurations - Main Page

To configure the launch configuration for the measurement of data:

Click the Trace and Profile tab.
Check the Enable Trace and Profile checkbox to enable the disabled options.
Figure 2. Debug Configurations - Trace and Profile Page (Kinetis Cortex M4 Core)

The table below describes the various Trace and Profile options.

Table 1. Trace and Profile Options for Kinetis Cortex M4 Core
Group	Option	Description
ETB		Embedded Trace Buffer where collected trace data is stored. For more information, refer Embedded Trace Buffer (ETB). NOTE: For K11D, K12D, K21D and K22D devices, ETB option is disabled because these devices do not have internal ETB buffer.
JTrace		Enables trace collection by using the Segger/J-Trace probe. For more information, refer J-Trace.
	Keep all trace buffers	Keeps all trace collected by the J-Trace or Tracelink (if Tracelink is selected) probe and not only the last buffer collected. NOTE: If you check this checkbox and collect trace, you might see some trace missing between buffers because of buffer overflow. A trace entry of Trace buffer read finished in the Trace Data viewer marks the point where an individual buffer ends. NOTE: This option is not the equivalent of continuous mode; in the Keep all trace buffers mode, all buffers are kept and concatenated, independent of one another. All data (including timestamps) is saved as if each buffer was collected alone, and timestamps for each appended buffer start from 0.
	TPIU	Trace Port Interface Unit - Collects ETM and ITM trace into the internal probe buffer of size 4MB. TPIU is a block on the processor that manages the output of trace. For more information, refer J-Trace.
	SWO	Serial Wire Output - Single pin serial output that collects only ITM trace into the buffer of size 4MB. SWO uses the Serial Wire Debug (SWD) debug connection. If selected, the Debug Port Interface should be set as SWD.
	Core clock	ARM core clock in Mhz needed for the serial connection setup. The core clock can change due to multiple settings. For example, when started, a K60 processor rated at 100Mh works at 25Mhz, which is the default value. You can change the core clock value according to the requirements.
Tracelink		Provides support of trace collection for 32-bit device architectures using the Tracelink (or multilink trace) probe. When selected, it provides the same options as JTrace.
Low Power Profiling		Allows monitoring of low power Wait states. This state lets peripherals to function, while allowing CPU to go to sleep reducing power. For more information, refer Low Power WAIT Mode.
Enable Logging		If checked, creates a log file that keeps details of the actions that took place while executing the target to collect trace data. For example, when the debug session terminated, when the target execution resumed or stopped.
Continuous Trace Collection		Allows you to collect continuous trace data when checked. That is, it stops the target in the background to read the trace every time the FIFO is almost full.
ETM		Enables/disables trace output from the Embedded Trace Macrocell (ETM) block. It controls the ETM port selection bit from ETM's control register. For more information, refer Embedded Trace Macrocell (ETM).
ETM	Collect Program Trace	Collects program trace.
ITM		Enables/disables trace output from the Instrumentation Trace Macrocell (ITM) block. For more information, refer Instrumentation Trace Macrocell (ITM).
	Collect Instrumentation trace	Collects instrumentation trace.
	Collect Profiling Counters	Enables/disables the following profiling counters at once: Cycle Count Event Generation - increments and generates synchronization and count events. Exception Trace - traces exception entry, exit and return to a pre-empted handler or thread. Exception Overhead Count - exception overhead counter counts the total cycles spent in exception processing. For example, entry stacking, return unstacking, or preemption. An event is emitted on counter overflow which occurs after every 256 cycles. CPI Count Sleep Overhead Count LSU Count - increments on the additional cycles required to execute all load and store instructions. Folded Instruction Count - increments on any instruction that executes in zero cycles.

The Kinetis K10/K20 50 Mhz and 72 MHz derivatives do not support ETB or ETM; they collect ITM trace only. Also, these derivatives do not support TPIU module; the only mode of collecting ITM trace is through SWO.

The probes that can collect trace on Kinetis K10/K20 50 Mhz and 72 MHz derivatives are J-Trace and J-link. You can debug but can not collect trace with P&E ARM Multilink. The Trace and Profile tab for these derivatives has only JTrace and ITM options enabled.

This topic contains the following sub-topics: