MM912F634 Ctrl Panel |  |
Last Error Message: |
General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2 General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2 General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2 General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2 General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2 General registers 1 General registers 2, SCI Timer 1 Timer 2, PWM ADC 1 ADC 2
0x00 | ISR(hi) Interrupt Source Register | 0 0 HOT LSOT HSOT LINOT SCI RX |  |  |  |  |
0x01 | ISR(lo) Interrupt Source Register | TX ERR TOV CH3 CH2 CH1 CH0 VSI |  |  |
0x02 | IVR Interrupt Vector Register | 0 0 IRQ IRQ IRQ IRQ IRQ IRQ |  |  |  |  |
0x04 | VCR Voltage Control Register | 0 0 0 0 |  |  |  |  |
0x05 | VSR Voltage Status Register | 0 0 0 0 HTC HVC LVC LBC |  |  |  |  |
0x08 | LXR Lx Status Register | 0 0 L5 L4 L3 L2 L1 L0 |  |  |  |  |
0x09 | LXCR Lx Control Register | 0 0 |  |  |  |  |
0x10 | WDR Watchdog Register | WDOFF WDWO 0 0 0 |  |  |  |  |
0x11 | WDSR Watchdog Service Register |  |  |  |  |  |
0x12 | WCR Wake Up Control Register |  |  |  |  |  |
0x13 | TCR Timing Control Register |  |  |  |  |  |
0x14 | WSR Wake Up Source Register | FWU LINWU L5WU L4WU L3WU L2WU L1WU L0WU |  |  |  |  |
0x15 | RSR Reset Status Register | 0 0 WDR EXR WUR LVRX LVR POR |  |  |  |  |
0x16 | MCR Mode Control Register | 0 0 0 0 0 0 |  |  |  |  |
0x18 | LINR LIN Register | LINOTC RX 0 |  |  |  |  |
0x20 | PTBC1 Port B Config Register 1 | 0 0 |  |  |  |  |
0x21 | PTBC2 Port B Config Register 2 | 0 0 0 0 |  |  |  |  |
0x22 | PTB Port B Data Register | 0 0 0 0 0 |  |  |  |  |
0x28 | HSCR High Side Control Register |  |  |  |  |  |
0x29 | HSSR High Side Status Register | HSOTC 0 0 0 HS2CL HS1CL HS2OL HS1OL |  |  |  |  |
0x30 | LSCR Low Side Control Register | 0 |  |  |  |  |
0x31 | LSSR Low Side Status Register | LSOTC 0 0 0 LS2CL LS1CL LS2OL LS1OL |  |  |  |  |
0x32 | LSEN Low Side Enable Register | 0 0 0 0 |  |  |  |  |
0x38 | HSR Hall Supply Register | HOTC 0 0 0 0 0 |  |  |  |  |
0x3C | CSR Current Sense Register | 0 0 0 |  |  |  |  |
0x40 | SCIBD(hi) SCI Baud Rate Register | 0 |  |  |  |  |
0x41 | SCIBD(lo) SCI Baud Rate Register |  |  |  |  |  |
0x42 | SCIC1 SCI Control Register 1 | 0 0 |  |  |  |  |
0x43 | SCIC2 SCI Control Register 2 |  |  |  |  |  |
0x44 | SCIS1 SCI Status Register 1 | TDRE TC RDRF IDLE OR NF FE PF |  |  |  |  |
0x45 | SCIS2 SCI Status Register 2 | 0 RAF |  |  |  |  |
0x46 | SCIC3 SCI Control Register 3 | R8 |  |  |  |  |
0x47 | SCID SCI Data Register |  |  |  |  |  |
0xC0 | TIOS Input Capture/Output Compare | 0 0 0 0 |  |  |  |  |
0xC1 | CFORC Timer Compare Force Register | 0 0 0 0 |  |  |  |  |
0xC2 | OC3M Output Compare 3 Mask Register | 0 0 0 0 |  |  |  |  |
0xC3 | OC3D Output Compare 3 Data Register | 0 0 0 0 |  |  |  |  |
0xC4 | TCNT(hi) Timer Count Register |  |  |  |  |  |
0xC5 | TCNT(lo) Timer Count Register |  |  |  |
0xC6 | TSCR1 Timer System Control Register 1 | 0 0 0 0 0 0 |  |  |  |  |
0xC7 | TTOV Timer Togle Overflow Register | 0 0 0 0 |  |  |  |  |
0xC8 | TCTL1 Timer Control Register 1 |  |  |  |  |  |
0xC9 | TCTL2 Timer Control Register 2 | 0 0 0 0 |  |  |  |  |
0xCA | TIE Timer Interrupt Enable Register |  |  |  |  |  |
0xCB | TSCR2 Timer System Control Register 2 | 0 0 0 |  |  |  |  |
0xCC | TFLG1 Main Timer Interrupt Flag 1 | 0 0 0 0 |  |  |  |  |
0xCD | TFLG2 Main Timer Interrupt Flag 2 | 0 0 0 0 0 0 0 |  |  |  |  |
0xCE | TC0(hi) Input Caupture/Output Compare 0 |  |  |  |  |  |
0xCF | TC0(lo) Input Caupture/Output Compare 0 |  |  |  |
0xD0 | TC1(hi) Input Caupture/Output Compare 1 |  |  |  |  |  |
0xD1 | TC1(lo) Input Caupture/Output Compare 1 |  |  |  |
0xD2 | TC2(hi) Input Caupture/Output Compare 2 |  |  |  |  |  |
0xD3 | TC2(lo) Input Caupture/Output Compare 2 |  |  |  |
0xD4 | TC3(hi) Input Caupture/Output Compare 3 |  |  |  |  |  |
0xD5 | TC3(lo) Input Caupture/Output Compare 3 |  |  |  |
0xD6 | TIMTST Timer Test Register | 0 0 0 0 0 0 0 |  |  |  |  |
0x60 | PWMCTL PWM Control Register |  |  |  |  |  |
0x61 | PWMPRCLK PWM Prescale Clock Register | 0 0 |  |  |  |  |
0x62 | PWMSCLA PWM Scale A Register |  |  |  |  |  |
0x63 | PWMSCLB PWM Scale B Register |  |  |  |  |  |
0x64 | PWMCNT0 PWM Channel Counter Register 0 |  |  |  |  |  |
0x65 | PWMCNT1 PWM Channel Counter Register 1 |  |  |  |  |  |
0x66 | PWMPER0 PWM Channel Period Register 0 |  |  |  |  |  |
0x67 | PWMPER1 PWM Channel Period Register 1 |  |  |  |  |  |
0x68 | PWMDTY0 PWM Channel Duty Register 0 |  |  |  |  |  |
0x69 | PWMDTY1 PWM Channel Duty Register 1 |  |  |  |  |  |
0x80 | ACR ADC Config Register | 0 |  |  |  |  |
0x81 | ASR ADC Status Register | SCF 2p5CLF 0 0 CCNT3 CCNT2 CCNT1 CCNT0 |  |  |  |  |
0x82 | ACCR(hi) ADC Conversion Control Register | 0 0 0 |  |  |  |  |
0x83 | ACCR(lo) ADC Conversion Control Register |  |  |  |
0x84 | ACCSR(hi) ADC Conversion Complete Register | CC15 0 0 0 CC11 CC10 CC9 CC8 |  |  |  |  |
0x85 | ACCSR(lo) ADC Conversion Complete Register | CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 |  |  |
0x86 | ADR0(hi) ADC Data Result Register 0 | adr0 9 adr0 8 adr0 7 adr0 6 adr0 5 adr0 4 adr0 3 adr0 2 |  |  |  |  |
0x87 | ADR0(lo) ADC Data Result Register 0 | adr0 1 adr0 0 0 0 0 0 0 0 |  |  |
0x88 | ADR1(hi) ADC Data Result Register 1 | adr1 9 adr1 8 adr1 7 adr1 6 adr1 5 adr1 4 adr1 3 adr1 2 |  |  |  |  |
0x89 | ADR1(lo) ADC Data Result Register 1 | adr1 1 adr1 0 0 0 0 0 0 0 |  |  |
0x8A | ADR2(hi) ADC Data Result Register 2 | adr2 9 adr2 8 adr2 7 adr2 6 adr2 5 adr2 4 adr2 3 adr2 2 |  |  |  |  |
0x8B | ADR2(lo) ADC Data Result Register 2 | adr2 1 adr2 0 0 0 0 0 0 0 |  |  |
0x8C | ADR3(hi) ADC Data Result Register 3 | adr3 9 adr3 8 adr3 7 adr3 6 adr3 5 adr3 4 adr3 3 adr3 2 |  |  |  |  |
0x8D | ADR3(lo) ADC Data Result Register 3 | adr3 1 adr3 0 0 0 0 0 0 0 |  |  |
0x8E | ADR4(hi) ADC Data Result Register 4 | adr4 9 adr4 8 adr4 7 adr4 6 adr4 5 adr4 4 adr4 3 adr4 2 |  |  |  |  |
0x8F | ADR4(lo) ADC Data Result Register 4 | adr4 1 adr4 0 0 0 0 0 0 0 |  |  |
0x90 | ADR5(hi) ADC Data Result Register 5 | adr5 9 adr5 8 adr5 7 adr5 6 adr5 5 adr5 4 adr5 3 adr5 2 |  |  |  |  |
0x91 | ADR5(lo) ADC Data Result Register 5 | adr5 1 adr5 0 0 0 0 0 0 0 |  |  |
0x92 | ADR6(hi) ADC Data Result Register 6 | adr6 9 adr6 8 adr6 7 adr6 6 adr6 5 adr6 4 adr6 3 adr6 2 |  |  |  |  |
0x93 | ADR6(lo) ADC Data Result Register 6 | adr6 1 adr6 0 0 0 0 0 0 0 |  |  |
0x94 | ADR7(hi) ADC Data Result Register 7 | adr7 9 adr7 8 adr7 7 adr7 6 adr7 5 adr7 4 adr7 3 adr7 2 |  |  |  |  |
0x95 | ADR7(lo) ADC Data Result Register 7 | adr7 1 adr7 0 0 0 0 0 0 0 |  |  |
0x96 | ADR8(hi) ADC Data Result Register 8 | adr8 9 adr8 8 adr8 7 adr8 6 adr8 5 adr8 4 adr8 3 adr8 2 |  |  |  |  |
0x97 | ADR8(lo) ADC Data Result Register 8 | adr8 1 adr8 0 0 0 0 0 0 0 |  |  |
0x98 | ADR9(hi) ADC Data Result Register 9 | adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 |  |  |  |  |
0x99 | ADR9(lo) ADC Data Result Register 9 | adr9 1 adr9 0 0 0 0 0 0 0 |  |  |
0x9A | ADR10(hi) ADC Data Result Register 10 | adr10 9 adr10 8 adr10 7 adr10 6 adr10 5 adr10 4 adr10 3 adr10 2 |  |  |  |  |
0x9B | ADR10(lo) ADC Data Result Register 10 | adr10 1 adr10 0 0 0 0 0 0 0 |  |  |
0x9C | ADR11(hi) ADC Data Result Register 11 | adr11 9 adr11 8 adr11 7 adr11 6 adr11 5 adr11 4 adr11 3 adr11 2 |  |  |  |  |
0x9D | ADR11(lo) ADC Data Result Register 11 | adr11 1 adr11 0 0 0 0 0 0 0 |  |  |
0xA4 | ADR15(hi) ADC Data Result Register 15 | adr15 9 adr15 8 adr15 7 adr15 6 adr15 5 adr15 4 adr15 3 adr15 2 |  |  |  |  |
0xA5 | ADR15(lo) ADC Data Result Register 15 | adr15 1 adr15 0 0 0 0 0 0 0 |  |  |

Legend: 0 - value always 0, bit not used - value not known XXX - value of the bit is 1 XXX - value of the bit is 0
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