ࡱ>   Root Entry Cache  Cells  X XParts  X X OrCAD Windows Library dQ`Q"Arial+x BlockModify1Courier New BlockModify1ST PART FIELD2ND PART FIELD3RD PART FIELD4TH PART FIELD5TH PART FIELD6TH PART FIELD7TH PART FIELD PCB Footprintddd00Views  X XLibrary6Symbols X $Types$CLASSICValuePart Reference`QMKL14Z32VLH4_LQFP64# -v`QMKL14Z32VLH4_LQFP64.Normal# -v`Q`Q`QGraphics X $Types$Packages X XExportBlocks X XCells Directory  2Parts Directory   9Views Directory  NetBundleMapData"  Symbols Directory$Graphics Directory&Packages Directory&2ExportBlocks Directory.`QMKL14Z32VLH4_LQFP64# -v`QMKL14Z32VLH4_LQFP64( U- \9MKL14Z32VLH4_LQFP64MKL14Z32VLH4_LQFP64.Normalt}<\9MKL14Z32VLH4_LQFP64.Normal0(( ||@9 \9VDD1!cati9 \9VSS1|!9 \9VDDA! : \9VREFH!: \9VREFL"|"!9 \9VSSA|!C \9PTE31/TPM0_CH4"&"!9 \9VDD3!9 \9VSS3|!9 \9VSS2|!9 \9VDD2!_ \9*PTE0/UART1_TX/RTC_CLKOUT/CMP0_OUT/I2C1_SDA&!_ \9*PTE1/SPI1_MOSI/UART1_RX/SPI1_MISO/I2C1_SCL&!a \9,PTE16/ADC0_SE1/SPI0_PCS0/UART2_TX/TPM_CLKIN0&!m \98PTE17/ADC0_SE5A/SPI0_SCK/UART2_RX/TPM_CLKIN1/LPTMR0_ALT3&!` \9+PTE18/ADC0_SE2/SPI0_MOSI/I2C0_SDA/SPI0_MISO&!a \9,PTE19/ADC0_SE6A/SPI0_MISO/I2C0_SCL/SPI0_MOSI&!U \9 PTE20/ADC0_SE0/TPM1_CH0/UART0_TX&!+xV \9!PTE21/ADC0_SE4A/TPM1_CH1/UART0_RX&!U \9 PTE22/ADC0_SE3/TPM2_CH0/UART2_TX&!L \9PTE24/TPM0_CH0/I2C0_SCL&!V \9!PTE23/ADC0_SE7A/TPM2_CH1/UART2_RX&!a \9,PTE29/CMP0_IN5/ADC0_SE4B/TPM0_CH2/TPM_CLKIN0&!a \9,PTE30/ADC0_SE23/CMP0_IN4/TPM0_CH3/TPM_CLKIN1&!L \9PTE25/TPM0_CH1/I2C0_SDA&!J \9PTA0/SWD_CLK/TPM0_CH5!K \9PTA1/UART0_RX/TPM2_CH0((!K \9PTA2/UART0_TX/TPM2_CH122!S \9PTA3/SWD_DIO/I2C1_SCL/TPM0_CH0<<!R \9PTA4/N\M\I\/I2C1_SDA/TPM0_CH1FF!B \9 PTA5/TPM0_CH2PP!C \9PTA12/TPM1_CH0ZZ!C \9PTA13/TPM1_CH1dd!U \9 PTA18/EXTAL0/UART1_RX/TPM_CLKIN0nn!` \9+PTA19/XTAL0/UART1_TX/TPM_CLKIN1/LPTMR0_ALT1xx!catE \9PTA20/R\E\S\E\T\!\ \9'PTB0/LLWU_P5/ADC0_SE8/I2C0_SCL/TPM1_CH0!T \9PTB1/ADC0_SE9/I2C0_SDA/TPM1_CH1!dexU \9 PTB2/ADC0_SE12/I2C0_SCL/TPM2_CH0!U \9 PTB3/ADC0_SE13/I2C0_SDA/TPM2_CH1!b \9-PTB16/SPI1_MOSI/UART0_RX/TPM_CLKIN0/SPI1_MISO!faontb \9-PTB17/SPI1_MISO/UART0_TX/TPM_CLKIN1/SPI1_MOSI!tcamiC \9PTB18/TPM2_CH0!C \9PTB19/TPM2_CH1!U \9 PTC0/ADC0_SE14/EXTRG_IN/CMP0_OUT!g \92PTC1/LLWU_P6/RTC_CLKIN/ADC0_SE15/I2C1_SCL/TPM0_CH0!U \9 PTC2/ADC0_SE11/I2C1_SDA/TPM0_CH1!alsioZ \9%PTC3/LLWU_P7/UART1_RX/TPM0_CH2/CLKOUT!o] \9(PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/TPM0_CH3""!_ \9*PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT,,!h \93PTC6/LLWU_P10/CMP0_IN0/SPI0_MOSI/EXTRG_IN/SPI0_MISO66!>V \9!PTC7/CMP0_IN1/SPI0_MISO/SPI0_MOSI@@!faT \9PTC8/CMP0_IN2/I2C0_SCL/TPM0_CH4JJ!T \9PTC9/CMP0_IN3/I2C0_SDA/TPM0_CH5TT!C \9PTC10/I2C1_SCL^^!+xC \9PTC11/I2C1_SDAhh!iL \9PTD0/SPI0_PCS0/TPM0_CH0&!U \9 PTD1/ADC0_SE5B/SPI0_SCK/TPM0_CH1(&(!@_ \9*PTD2/SPI0_MOSI/UART2_RX/TPM0_CH2/SPI0_MISO2&2!_ \9*PTD3/SPI0_MISO/UART2_TX/TPM0_CH3/SPI0_MOSI<&<! ^ \9)PTD4/LLWU_P14/SPI1_PCS0/UART2_RX/TPM0_CH4F&F!tpion^ \9)PTD5/ADC0_SE6B/SPI1_SCK/UART2_TX/TPM0_CH5P&P!i \94PTD6/LLWU_P15/ADC0_SE7B/SPI1_MOSI/UART0_RX/SPI1_MISOZ&Z!iV \9!PTD7/SPI1_MISO/UART0_TX/SPI1_MOSId&d!A'"' '\9|0'"' '\90lU- \9MKL14Z32VLH4_LQFP64U  \9MKL14Z32VLH4_LQFP64@34131415161948473130125678910112012171821222324252627282932333435363738394041424344454649505152535455565758596061626364