LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
Data Structures | Macros | Enumerations | Functions
CHIP: LPC1125 A/D conversion driver

Detailed Description

The LPC1125 ADC is different than other LPC11xx ADC peripherals and has a different API than the other LPC11xx ADC driver. The LCP1125 only supports ADC channels 1-8.

Data Structures

struct  LPC_ADC_T
 ADC register block structure. More...
 

Macros

#define ADC_MAX_SAMPLE_RATE   2000000
 
#define ADC_CR_CLKDIV_MASK   (0xFF << 0)
 ADC register support bitfields and mask. More...
 
#define ADC_CR_CLKDIV_BITPOS   (0)
 
#define ADC_CR_ASYNC_MODE   (1 << 8)
 
#define ADC_CR_MODE10BIT   (1 << 9)
 
#define ADC_CR_LPWRMODEBIT   (1 << 10)
 
#define ADC_CR_CALMODEBIT   (1 << 30)
 
#define ADC_CR_BITACC(n)   ((((n) & 0x1) << 9))
 
#define ADC_CR_CLKDIV(n)   ((((n) & 0xFF) << 0))
 
#define ADC_SAMPLE_RATE_CONFIG_MASK   (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01))
 
#define ADC_SEQ_CTRL_CHANSEL(n)   (1 << (n))
 
#define ADC_SEQ_CTRL_CHANSEL_MASK   (0xFFF)
 
#define ADC_SEQ_CTRL_HWTRIG_ARM_TXEV   (0 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT3   (1 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT2   (2 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_PIO0_2   (3 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_PIO0_7   (4 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_PIO0_8   (5 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_PIO0_9   (6 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_PIO2_0   (7 << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_MASK   (0x3F << 12)
 
#define ADC_SEQ_CTRL_HWTRIG_POLPOS   (1 << 18)
 
#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS   (1 << 19)
 
#define ADC_SEQ_CTRL_START   (1 << 26)
 
#define ADC_SEQ_CTRL_BURST   (1 << 27)
 
#define ADC_SEQ_CTRL_SINGLESTEP   (1 << 28)
 
#define ADC_SEQ_CTRL_LOWPRIO   (1 << 29)
 
#define ADC_SEQ_CTRL_MODE_EOS   (1 << 30)
 
#define ADC_SEQ_CTRL_SEQ_ENA   (1UL << 31)
 
#define ADC_SEQ_GDAT_RESULT_MASK   (0xFFF << 4)
 
#define ADC_SEQ_GDAT_RESULT_BITPOS   (4)
 
#define ADC_SEQ_GDAT_THCMPRANGE_MASK   (0x3 << 16)
 
#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS   (16)
 
#define ADC_SEQ_GDAT_THCMPCROSS_MASK   (0x3 << 18)
 
#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS   (18)
 
#define ADC_SEQ_GDAT_CHAN_MASK   (0xF << 26)
 
#define ADC_SEQ_GDAT_CHAN_BITPOS   (26)
 
#define ADC_SEQ_GDAT_OVERRUN   (1 << 30)
 
#define ADC_SEQ_GDAT_DATAVALID   (1UL << 31)
 
#define ADC_DR_RESULT(n)   ((((n) >> 4) & 0xFFF))
 
#define ADC_DR_THCMPRANGE_MASK   (0x3 << 16)
 
#define ADC_DR_THCMPRANGE_BITPOS   (16)
 
#define ADC_DR_THCMPRANGE(n)   (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3)
 
#define ADC_DR_THCMPCROSS_MASK   (0x3 << 18)
 
#define ADC_DR_THCMPCROSS_BITPOS   (18)
 
#define ADC_DR_THCMPCROSS(n)   (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3)
 
#define ADC_DR_CHAN_MASK   (0xF << 26)
 
#define ADC_DR_CHAN_BITPOS   (26)
 
#define ADC_DR_CHANNEL(n)   (((n) >> ADC_DR_CHAN_BITPOS) & 0xF)
 
#define ADC_DR_OVERRUN   (1 << 30)
 
#define ADC_DR_DATAVALID   (1UL << 31)
 
#define ADC_DR_DONE(n)   (((n) >> 31))
 
#define ADC_THR_VAL_MASK   (0xFFF << 4)
 
#define ADC_THR_VAL_POS   (4)
 
#define ADC_THRSEL_CHAN_SEL_THR1(n)   (1 << (n))
 
#define ADC_INTEN_SEQA_ENABLE   (1 << 0)
 
#define ADC_INTEN_SEQB_ENABLE   (1 << 1)
 
#define ADC_INTEN_SEQN_ENABLE(seq)   (1 << (seq))
 
#define ADC_INTEN_OVRRUN_ENABLE   (1 << 2)
 
#define ADC_INTEN_CMP_DISBALE   (0)
 
#define ADC_INTEN_CMP_OUTSIDETH   (1)
 
#define ADC_INTEN_CMP_CROSSTH   (2)
 
#define ADC_INTEN_CMP_MASK   (3)
 
#define ADC_INTEN_CMP_ENABLE(isel, ch)   (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3))
 
#define ADC_FLAGS_THCMP_MASK(ch)   (1 << (ch))
 
#define ADC_FLAGS_OVRRUN_MASK(ch)   (1 << (12 + (ch)))
 
#define ADC_FLAGS_SEQA_OVRRUN_MASK   (1 << 24)
 
#define ADC_FLAGS_SEQB_OVRRUN_MASK   (1 << 25)
 
#define ADC_FLAGS_SEQN_OVRRUN_MASK(seq)   (1 << (24 + (seq)))
 
#define ADC_FLAGS_SEQA_INT_MASK   (1 << 28)
 
#define ADC_FLAGS_SEQB_INT_MASK   (1 << 29)
 
#define ADC_FLAGS_SEQN_INT_MASK(seq)   (1 << (28 + (seq)))
 
#define ADC_FLAGS_THCMP_INT_MASK   (1 << 30)
 
#define ADC_FLAGS_OVRRUN_INT_MASK   (1UL << 31)
 
#define ADC_TRIM_VRANGE_HIGHV   (0 << 5)
 
#define ADC_TRIM_VRANGE_LOWV   (1 << 5)
 

Enumerations

enum  ADC_SEQ_IDX_T { ADC_SEQA_IDX, ADC_SEQB_IDX }
 
enum  ADC_DR_THCMPRANGE_T { ADC_DR_THCMPRANGE_INRANGE, ADC_DR_THCMPRANGE_RESERVED, ADC_DR_THCMPRANGE_BELOW, ADC_DR_THCMPRANGE_ABOVE }
 
enum  ADC_DR_THCMPCROSS_T { ADC_DR_THCMPCROSS_NOCROSS, ADC_DR_THCMPCROSS_RESERVED, ADC_DR_THCMPCROSS_DOWNWARD, ADC_DR_THCMPCROSS_UPWARD }
 
enum  ADC_INTEN_THCMP_T { ADC_INTEN_THCMP_DISABLE, ADC_INTEN_THCMP_OUTSIDE, ADC_INTEN_THCMP_CROSSING }
 

Functions

void Chip_ADC_Init (LPC_ADC_T *pADC, uint32_t flags)
 Initialize the ADC peripheral. More...
 
void Chip_ADC_DeInit (LPC_ADC_T *pADC)
 Shutdown ADC. More...
 
STATIC INLINE void Chip_ADC_SetDivider (LPC_ADC_T *pADC, uint8_t div)
 Set ADC divider. More...
 
void Chip_ADC_SetClockRate (LPC_ADC_T *pADC, uint32_t rate)
 Set ADC clock rate. More...
 
STATIC INLINE uint8_t Chip_ADC_GetDivider (LPC_ADC_T *pADC)
 Get ADC divider. More...
 
void Chip_ADC_StartCalibration (LPC_ADC_T *pADC)
 Start ADC calibration. More...
 
STATIC INLINE bool Chip_ADC_IsCalibrationDone (LPC_ADC_T *pADC)
 Start ADC calibration. More...
 
void Chip_ADC_SetSequencerBits (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
 Helper function for safely setting ADC sequencer register bits. More...
 
void Chip_ADC_ClearSequencerBits (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
 Helper function for safely clearing ADC sequencer register bits. More...
 
STATIC INLINE void Chip_ADC_SetupSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t options)
 Sets up ADC conversion sequencer A or B. More...
 
STATIC INLINE void Chip_ADC_EnableSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Enables a sequencer. More...
 
STATIC INLINE void Chip_ADC_DisableSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Disables a sequencer. More...
 
STATIC INLINE void Chip_ADC_StartSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Forces a sequencer trigger event (software trigger of ADC) More...
 
STATIC INLINE void Chip_ADC_StartBurstSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Starts sequencer burst mode. More...
 
STATIC INLINE void Chip_ADC_StopBurstSequencer (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Stops sequencer burst mode. More...
 
STATIC INLINE uint32_t Chip_ADC_GetSequencerDataReg (LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex)
 Read a ADC sequence global data register. More...
 
STATIC INLINE uint32_t Chip_ADC_GetDataReg (LPC_ADC_T *pADC, uint8_t index)
 Read a ADC data register. More...
 
STATIC INLINE void Chip_ADC_SetThrLowValue (LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value)
 Set Threshold low value in ADC. More...
 
STATIC INLINE void Chip_ADC_SetThrHighValue (LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value)
 Set Threshold high value in ADC. More...
 
void Chip_ADC_SelectTH0Channels (LPC_ADC_T *pADC, uint32_t channels)
 Select threshold 0 values for comparison for selected channels. More...
 
void Chip_ADC_SelectTH1Channels (LPC_ADC_T *pADC, uint32_t channels)
 Select threshold 1 value for comparison for selected channels. More...
 
void Chip_ADC_EnableInt (LPC_ADC_T *pADC, uint32_t intMask)
 Enable interrupts in ADC (sequencers A/B and overrun) More...
 
void Chip_ADC_DisableInt (LPC_ADC_T *pADC, uint32_t intMask)
 Disable interrupts in ADC (sequencers A/B and overrun) More...
 
void Chip_ADC_SetThresholdInt (LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt)
 Enable a threshold event interrupt in ADC. More...
 
STATIC INLINE uint32_t Chip_ADC_GetFlags (LPC_ADC_T *pADC)
 Get flags register in ADC. More...
 
STATIC INLINE void Chip_ADC_ClearFlags (LPC_ADC_T *pADC, uint32_t flags)
 Clear flags register in ADC. More...
 
STATIC INLINE void Chip_ADC_SetTrim (LPC_ADC_T *pADC, uint32_t trim)
 Set Trim register in ADC. More...
 

Macro Definition Documentation

#define ADC_CR_ASYNC_MODE   (1 << 8)

Asynchronous mode enable bit

Definition at line 82 of file adc_112x.h.

#define ADC_CR_BITACC (   n)    ((((n) & 0x1) << 9))

12-bit or 10-bit ADC accuracy

Definition at line 86 of file adc_112x.h.

#define ADC_CR_CALMODEBIT   (1 << 30)

Self calibration cycle enable bit

Definition at line 85 of file adc_112x.h.

#define ADC_CR_CLKDIV (   n)    ((((n) & 0xFF) << 0))

The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D

Definition at line 87 of file adc_112x.h.

#define ADC_CR_CLKDIV_BITPOS   (0)

Bit position for Clock divider value

Definition at line 81 of file adc_112x.h.

#define ADC_CR_CLKDIV_MASK   (0xFF << 0)

ADC register support bitfields and mask.

ADC Control register bit fields Mask for Clock divider value

Definition at line 80 of file adc_112x.h.

#define ADC_CR_LPWRMODEBIT   (1 << 10)

Low power mode enable bit

Definition at line 84 of file adc_112x.h.

#define ADC_CR_MODE10BIT   (1 << 9)

10-bit mode enable bit

Definition at line 83 of file adc_112x.h.

#define ADC_DR_CHAN_BITPOS   (26)

Channel number bit position

Definition at line 136 of file adc_112x.h.

#define ADC_DR_CHAN_MASK   (0xF << 26)

Channel number mask

Definition at line 135 of file adc_112x.h.

#define ADC_DR_CHANNEL (   n)    (((n) >> ADC_DR_CHAN_BITPOS) & 0xF)

Channel number bit position

Definition at line 137 of file adc_112x.h.

#define ADC_DR_DATAVALID   (1UL << 31)

Data valid bit

Definition at line 139 of file adc_112x.h.

#define ADC_DR_DONE (   n)    (((n) >> 31))

Definition at line 140 of file adc_112x.h.

#define ADC_DR_OVERRUN   (1 << 30)

Overrun bit

Definition at line 138 of file adc_112x.h.

#define ADC_DR_RESULT (   n)    ((((n) >> 4) & 0xFFF))

ADC Data register bit fields Macro for getting the ADC data value

Definition at line 128 of file adc_112x.h.

#define ADC_DR_THCMPCROSS (   n)    (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3)

Definition at line 134 of file adc_112x.h.

#define ADC_DR_THCMPCROSS_BITPOS   (18)

Comparison cross bit position

Definition at line 133 of file adc_112x.h.

#define ADC_DR_THCMPCROSS_MASK   (0x3 << 18)

Comparion cross mask

Definition at line 132 of file adc_112x.h.

#define ADC_DR_THCMPRANGE (   n)    (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3)

Definition at line 131 of file adc_112x.h.

#define ADC_DR_THCMPRANGE_BITPOS   (16)

Comparison range bit position

Definition at line 130 of file adc_112x.h.

#define ADC_DR_THCMPRANGE_MASK   (0x3 << 16)

Comparion range mask

Definition at line 129 of file adc_112x.h.

#define ADC_FLAGS_OVRRUN_INT_MASK   (1UL << 31)

Overrun Interrupt status

Definition at line 170 of file adc_112x.h.

#define ADC_FLAGS_OVRRUN_MASK (   ch)    (1 << (12 + (ch)))

Overrun status for channel

Definition at line 162 of file adc_112x.h.

#define ADC_FLAGS_SEQA_INT_MASK   (1 << 28)

Seq A Interrupt status

Definition at line 166 of file adc_112x.h.

#define ADC_FLAGS_SEQA_OVRRUN_MASK   (1 << 24)

Seq A Overrun status

Definition at line 163 of file adc_112x.h.

#define ADC_FLAGS_SEQB_INT_MASK   (1 << 29)

Seq B Interrupt status

Definition at line 167 of file adc_112x.h.

#define ADC_FLAGS_SEQB_OVRRUN_MASK   (1 << 25)

Seq B Overrun status

Definition at line 164 of file adc_112x.h.

#define ADC_FLAGS_SEQN_INT_MASK (   seq)    (1 << (28 + (seq)))

Seq A/B Interrupt status

Definition at line 168 of file adc_112x.h.

#define ADC_FLAGS_SEQN_OVRRUN_MASK (   seq)    (1 << (24 + (seq)))

Seq A/B Overrun status

Definition at line 165 of file adc_112x.h.

#define ADC_FLAGS_THCMP_INT_MASK   (1 << 30)

Threshold comparison Interrupt status

Definition at line 169 of file adc_112x.h.

#define ADC_FLAGS_THCMP_MASK (   ch)    (1 << (ch))

ADC Flags register bit fields Threshold comparison status for channel

Definition at line 161 of file adc_112x.h.

#define ADC_INTEN_CMP_CROSSTH   (2)

Crossing threshold interrupt value

Definition at line 156 of file adc_112x.h.

#define ADC_INTEN_CMP_DISBALE   (0)

Disable comparison interrupt value

Definition at line 154 of file adc_112x.h.

#define ADC_INTEN_CMP_ENABLE (   isel,
  ch 
)    (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3))

Interrupt selection for channel

Definition at line 158 of file adc_112x.h.

#define ADC_INTEN_CMP_MASK   (3)

Comparison interrupt value mask

Definition at line 157 of file adc_112x.h.

#define ADC_INTEN_CMP_OUTSIDETH   (1)

Outside threshold interrupt value

Definition at line 155 of file adc_112x.h.

#define ADC_INTEN_OVRRUN_ENABLE   (1 << 2)

Overrun Interrupt enable bit

Definition at line 153 of file adc_112x.h.

#define ADC_INTEN_SEQA_ENABLE   (1 << 0)

ADC Interrupt Enable register bit fields Sequence A Interrupt enable bit

Definition at line 150 of file adc_112x.h.

#define ADC_INTEN_SEQB_ENABLE   (1 << 1)

Sequence B Interrupt enable bit

Definition at line 151 of file adc_112x.h.

#define ADC_INTEN_SEQN_ENABLE (   seq)    (1 << (seq))

Sequence A/B Interrupt enable bit

Definition at line 152 of file adc_112x.h.

#define ADC_MAX_SAMPLE_RATE   2000000

Maximum sample rate in Hz (12-bit conversions)

Definition at line 74 of file adc_112x.h.

#define ADC_SAMPLE_RATE_CONFIG_MASK   (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01))

Definition at line 88 of file adc_112x.h.

#define ADC_SEQ_CTRL_BURST   (1 << 27)

Repeated conversion enable bit

Definition at line 109 of file adc_112x.h.

#define ADC_SEQ_CTRL_CHANSEL (   n)    (1 << (n))

ADC Sequence Control register bit fields Channel select macro

Definition at line 91 of file adc_112x.h.

#define ADC_SEQ_CTRL_CHANSEL_MASK   (0xFFF)

Channel select mask

Definition at line 92 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_ARM_TXEV   (0 << 12)

ADC hardware trigger sources in SEQ_CTRL HW trigger input - ARM TXEV

Definition at line 95 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT2   (2 << 12)

HW trigger input - Match output 2 of CT16B1

Definition at line 97 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT3   (1 << 12)

HW trigger input - Match output 3 of CT16B1

Definition at line 96 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_MASK   (0x3F << 12)

HW trigger input bitfield mask

Definition at line 103 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_PIO0_2   (3 << 12)

HW trigger input - PIO0_2

Definition at line 98 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_PIO0_7   (4 << 12)

HW trigger input - PIO0_7

Definition at line 99 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_PIO0_8   (5 << 12)

HW trigger input - PIO0_8

Definition at line 100 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_PIO0_9   (6 << 12)

HW trigger input - PIO0_9

Definition at line 101 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_PIO2_0   (7 << 12)

HW trigger input - PIO2_0

Definition at line 102 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_POLPOS   (1 << 18)

SEQ_CTRL register bit fields HW trigger polarity - positive edge

Definition at line 106 of file adc_112x.h.

#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS   (1 << 19)

HW trigger bypass synchronisation

Definition at line 107 of file adc_112x.h.

#define ADC_SEQ_CTRL_LOWPRIO   (1 << 29)

High priority enable bit (regardless of name)

Definition at line 111 of file adc_112x.h.

#define ADC_SEQ_CTRL_MODE_EOS   (1 << 30)

Mode End of sequence enable bit

Definition at line 112 of file adc_112x.h.

#define ADC_SEQ_CTRL_SEQ_ENA   (1UL << 31)

Sequence enable bit

Definition at line 113 of file adc_112x.h.

#define ADC_SEQ_CTRL_SINGLESTEP   (1 << 28)

Single step enable bit

Definition at line 110 of file adc_112x.h.

#define ADC_SEQ_CTRL_START   (1 << 26)

Start conversion enable bit

Definition at line 108 of file adc_112x.h.

#define ADC_SEQ_GDAT_CHAN_BITPOS   (26)

Channel number bit position

Definition at line 123 of file adc_112x.h.

#define ADC_SEQ_GDAT_CHAN_MASK   (0xF << 26)

Channel number mask

Definition at line 122 of file adc_112x.h.

#define ADC_SEQ_GDAT_DATAVALID   (1UL << 31)

Data valid bit

Definition at line 125 of file adc_112x.h.

#define ADC_SEQ_GDAT_OVERRUN   (1 << 30)

Overrun bit

Definition at line 124 of file adc_112x.h.

#define ADC_SEQ_GDAT_RESULT_BITPOS   (4)

Result start bit position

Definition at line 117 of file adc_112x.h.

#define ADC_SEQ_GDAT_RESULT_MASK   (0xFFF << 4)

ADC global data register bit fields Result value mask

Definition at line 116 of file adc_112x.h.

#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS   (18)

Comparison cross bit position

Definition at line 121 of file adc_112x.h.

#define ADC_SEQ_GDAT_THCMPCROSS_MASK   (0x3 << 18)

Comparion cross mask

Definition at line 120 of file adc_112x.h.

#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS   (16)

Comparison range bit position

Definition at line 119 of file adc_112x.h.

#define ADC_SEQ_GDAT_THCMPRANGE_MASK   (0x3 << 16)

Comparion range mask

Definition at line 118 of file adc_112x.h.

#define ADC_THR_VAL_MASK   (0xFFF << 4)

ADC low/high Threshold register bit fields Threshold value bit mask

Definition at line 143 of file adc_112x.h.

#define ADC_THR_VAL_POS   (4)

Threshold value bit position

Definition at line 144 of file adc_112x.h.

#define ADC_THRSEL_CHAN_SEL_THR1 (   n)    (1 << (n))

ADC Threshold select register bit fields Select THR1 register for channel n

Definition at line 147 of file adc_112x.h.

#define ADC_TRIM_VRANGE_HIGHV   (0 << 5)

ADC Trim register bit fields Voltage range bit - High volatge (2.7V to 3.6V)

Definition at line 173 of file adc_112x.h.

#define ADC_TRIM_VRANGE_LOWV   (1 << 5)

Voltage range bit - Low volatge (1.8V to 2.7V)

Definition at line 174 of file adc_112x.h.

Enumeration Type Documentation

ADC sequence global data register threshold comparison cross enumerations

Enumerator
ADC_DR_THCMPCROSS_NOCROSS 
ADC_DR_THCMPCROSS_RESERVED 
ADC_DR_THCMPCROSS_DOWNWARD 
ADC_DR_THCMPCROSS_UPWARD 

Definition at line 377 of file adc_112x.h.

ADC sequence global data register threshold comparison range enumerations

Enumerator
ADC_DR_THCMPRANGE_INRANGE 
ADC_DR_THCMPRANGE_RESERVED 
ADC_DR_THCMPRANGE_BELOW 
ADC_DR_THCMPRANGE_ABOVE 

Definition at line 369 of file adc_112x.h.

Threshold interrupt event options

Enumerator
ADC_INTEN_THCMP_DISABLE 
ADC_INTEN_THCMP_OUTSIDE 
ADC_INTEN_THCMP_CROSSING 

Definition at line 495 of file adc_112x.h.

Sequence index enumerations, used in various parts of the code for register indexing and sequencer selection

Enumerator
ADC_SEQA_IDX 
ADC_SEQB_IDX 

Definition at line 49 of file adc_112x.h.

Function Documentation

STATIC INLINE void Chip_ADC_ClearFlags ( LPC_ADC_T pADC,
uint32_t  flags 
)

Clear flags register in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
flags: An Or'ed values of ADC_FLAGS_* values to clear
Returns
Flags register value (ORed ADC_FLAG* values)

Definition at line 530 of file adc_112x.h.

void Chip_ADC_ClearSequencerBits ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex,
uint32_t  bits 
)

Helper function for safely clearing ADC sequencer register bits.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to clear bits for
bits: Or'ed bits of a sequencer register to clear
Returns
Nothing
Note
This function will safely clear the ADC sequencer register bits while maintaining bits 20..25 as 0, regardless of the read state of those bits.

Definition at line 173 of file adc_112x.c.

void Chip_ADC_DeInit ( LPC_ADC_T pADC)

Shutdown ADC.

Parameters
pADC: The base of ADC peripheral on the chip
Returns
Nothing
Note
Disables the ADC clocks and ADC power

Definition at line 116 of file adc_112x.c.

void Chip_ADC_DisableInt ( LPC_ADC_T pADC,
uint32_t  intMask 
)

Disable interrupts in ADC (sequencers A/B and overrun)

Parameters
pADC: The base of ADC peripheral on the chip
intMask: Interrupt values to be disabled (see notes)
Returns
None
Note
Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to disable the specific ADC interrupts.

Definition at line 191 of file adc_112x.c.

STATIC INLINE void Chip_ADC_DisableSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Disables a sequencer.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to disable
Returns
Nothing

Definition at line 325 of file adc_112x.h.

void Chip_ADC_EnableInt ( LPC_ADC_T pADC,
uint32_t  intMask 
)

Enable interrupts in ADC (sequencers A/B and overrun)

Parameters
pADC: The base of ADC peripheral on the chip
intMask: Interrupt values to be enabled (see notes)
Returns
None
Note
Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to enable the specific ADC interrupts.

Definition at line 185 of file adc_112x.c.

STATIC INLINE void Chip_ADC_EnableSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Enables a sequencer.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to enable
Returns
Nothing

Definition at line 314 of file adc_112x.h.

STATIC INLINE uint32_t Chip_ADC_GetDataReg ( LPC_ADC_T pADC,
uint8_t  index 
)

Read a ADC data register.

Parameters
pADC: The base of ADC peripheral on the chip
index: Data register to read, 1-8
Returns
Current raw value of the ADC data register
Note
This function returns the raw value of the data register and clears the overrun and datavalid status for the register. Once this register is read, the following functions can be used to parse the raw value:
uint32_t adcDataRawValue = Chip_ADC_ReadSequencerDataReg(LPC_ADC, ADC_SEQA_IDX); // Get raw value uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag

Definition at line 421 of file adc_112x.h.

STATIC INLINE uint8_t Chip_ADC_GetDivider ( LPC_ADC_T pADC)

Get ADC divider.

Parameters
pADC: The base of ADC peripheral on the chip
Returns
the current ADC divider
Note
This function returns the divider that is used to generate the ADC frequency. The returned value must be incremented by 1. The frequency can be determined with the following function:
adc_freq = Chip_Clock_GetSystemClockRate() / (Chip_ADC_GetDivider(LPC_ADC) + 1);

Definition at line 233 of file adc_112x.h.

STATIC INLINE uint32_t Chip_ADC_GetFlags ( LPC_ADC_T pADC)

Get flags register in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
Returns
Flags register value (ORed ADC_FLAG* values)
Note
Mask the return value of this function with the ADC_FLAGS_* definitions to determine the overall ADC interrupt events.
Example:
if (Chip_ADC_GetFlags(LPC_ADC) & ADC_FLAGS_THCMP_MASK(3) // Check of threshold comp status for ADC channel 3

Definition at line 519 of file adc_112x.h.

STATIC INLINE uint32_t Chip_ADC_GetSequencerDataReg ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Read a ADC sequence global data register.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to read
Returns
Current raw value of the ADC sequence A or B global data register
Note
This function returns the raw value of the data register and clears the overrun and datavalid status for the register. Once this register is read, the following functions can be used to parse the raw value:
uint32_t adcDataRawValue = Chip_ADC_ReadSequencerDataReg(LPC_ADC, ADC_SEQA_IDX); // Get raw value uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag

Definition at line 400 of file adc_112x.h.

void Chip_ADC_Init ( LPC_ADC_T pADC,
uint32_t  flags 
)

Initialize the ADC peripheral.

Parameters
pADC: The base of ADC peripheral on the chip
flags: ADC flags for init (ADC_CR_MODE10BIT and/or ADC_CR_LPWRMODEBIT)
Returns
Nothing
Note
To select low-power ADC mode, enable the ADC_CR_LPWRMODEBIT flag. To select 10-bit conversion mode, enable the ADC_CR_MODE10BIT flag.
Example: Chip_ADC_Init(LPC_ADC, (ADC_CR_MODE10BIT | ADC_CR_LPWRMODEBIT));

Definition at line 99 of file adc_112x.c.

STATIC INLINE bool Chip_ADC_IsCalibrationDone ( LPC_ADC_T pADC)

Start ADC calibration.

Parameters
pADC: The base of ADC peripheral on the chip
Returns
TRUE if calibration is complete, otherwise FALSE.

Definition at line 253 of file adc_112x.h.

void Chip_ADC_SelectTH0Channels ( LPC_ADC_T pADC,
uint32_t  channels 
)

Select threshold 0 values for comparison for selected channels.

Parameters
pADC: The base of ADC peripheral on the chip
channels: An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values
Returns
None
Note
Select multiple channels to use the threshold 0 comparison.
Example:
Chip_ADC_SelectTH0Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(1) | ADC_THRSEL_CHAN_SEL_THR1(2))); // Selects channels 1 and 2 for threshold 0

Definition at line 209 of file adc_112x.c.

void Chip_ADC_SelectTH1Channels ( LPC_ADC_T pADC,
uint32_t  channels 
)

Select threshold 1 value for comparison for selected channels.

Parameters
pADC: The base of ADC peripheral on the chip
channels: An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values
Returns
None
Note
Select multiple channels to use the 1 threshold comparison.
Example:
Chip_ADC_SelectTH1Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(4) | ADC_THRSEL_CHAN_SEL_THR1(5))); // Selects channels 4 and 5 for 1 threshold

Definition at line 215 of file adc_112x.c.

void Chip_ADC_SetClockRate ( LPC_ADC_T pADC,
uint32_t  rate 
)

Set ADC clock rate.

Parameters
pADC: The base of ADC peripheral on the chip
rate: rate in Hz to set ADC clock to (maximum ADC_MAX_SAMPLE_RATE)
Returns
Nothing

Definition at line 127 of file adc_112x.c.

STATIC INLINE void Chip_ADC_SetDivider ( LPC_ADC_T pADC,
uint8_t  div 
)

Set ADC divider.

Parameters
pADC: The base of ADC peripheral on the chip
div: ADC divider value to set minus 1
Returns
Nothing
Note
The value is used as a divider to generate the ADC clock rate from the ADC input clock. The ADC input clock is based on the system clock. Valid values for this function are from 0 to 255 with 0=divide by 1, 1=divide by 2, 2=divide by 3, etc.
Do not decrement this value by 1.
To set the ADC clock rate to 1MHz, use the following function:
Chip_ADC_SetDivider(LPC_ADC, (Chip_Clock_GetSystemClockRate() / 1000000) - 1);

Definition at line 208 of file adc_112x.h.

void Chip_ADC_SetSequencerBits ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex,
uint32_t  bits 
)

Helper function for safely setting ADC sequencer register bits.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to set bits for
bits: Or'ed bits of a sequencer register to set
Returns
Nothing
Note
This function will safely set the ADC sequencer register bits while maintaining bits 20..25 as 0, regardless of the read state of those bits.

Definition at line 161 of file adc_112x.c.

void Chip_ADC_SetThresholdInt ( LPC_ADC_T pADC,
uint8_t  ch,
ADC_INTEN_THCMP_T  thInt 
)

Enable a threshold event interrupt in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
ch: ADC channel to set threshold inetrrupt for, 1-8
thInt: Selected threshold interrupt type
Returns
None

Definition at line 197 of file adc_112x.c.

STATIC INLINE void Chip_ADC_SetThrHighValue ( LPC_ADC_T pADC,
uint8_t  thrnum,
uint16_t  value 
)

Set Threshold high value in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
thrnum: Threshold register value (1 for threshold register 1, 0 for threshold register 0)
value: Threshold high data value (should be 12-bit value)
Returns
None

Definition at line 445 of file adc_112x.h.

STATIC INLINE void Chip_ADC_SetThrLowValue ( LPC_ADC_T pADC,
uint8_t  thrnum,
uint16_t  value 
)

Set Threshold low value in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
thrnum: Threshold register value (1 for threshold register 1, 0 for threshold register 0)
value: Threshold low data value (should be 12-bit value)
Returns
None

Definition at line 433 of file adc_112x.h.

STATIC INLINE void Chip_ADC_SetTrim ( LPC_ADC_T pADC,
uint32_t  trim 
)

Set Trim register in ADC.

Parameters
pADC: The base of ADC peripheral on the chip
trim: Trim value (ADC_TRIM_VRANGE_HIGHV or ADC_TRIM_VRANGE_LOWV)
Returns
None

Definition at line 541 of file adc_112x.h.

STATIC INLINE void Chip_ADC_SetupSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex,
uint32_t  options 
)

Sets up ADC conversion sequencer A or B.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to setup
options: OR'ed Sequencer options to setup (see notes)
Returns
Nothing
Note
Sets up sequencer options for a conversion sequence. This function should be used to setup the selected channels for the sequence, the sequencer trigger, the trigger polarity, synchronization bypass, priority, and mode. All options are passed to the functions as a OR'ed list of values. This function will disable/clear the sequencer start/burst/single step/enable if they are enabled.
Select the channels by OR'ing in one or more ADC_SEQ_CTRL_CHANSEL(ch) values.
Select the hardware trigger by OR'ing in one ADC_SEQ_CTRL_HWTRIG_* value.
Select a positive edge hardware trigger by OR'ing in ADC_SEQ_CTRL_HWTRIG_POLPOS.
Select trigger bypass synchronisation by OR'ing in ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS.
Select ADC single step on trigger/start by OR'ing in ADC_SEQ_CTRL_SINGLESTEP.
Select higher priority conversion on the other sequencer by OR'ing in ADC_SEQ_CTRL_LOWPRIO.
Select end of seqeuence instead of end of conversion interrupt by OR'ing in ADC_SEQ_CTRL_MODE_EOS.
Example for setting up sequencer A (channels 0-2, trigger on high edge of PIO0_2, interrupt on end of sequence):
Chip_ADC_SetupSequencer(LPC_ADC, ADC_SEQA_IDX, ( ADC_SEQ_CTRL_CHANSEL(0) | ADC_SEQ_CTRL_CHANSEL(1) | ADC_SEQ_CTRL_CHANSEL(2) | ADC_SEQ_CTRL_HWTRIG_PIO0_2 | ADC_SEQ_CTRL_HWTRIG_POLPOS | ADC_SEQ_CTRL_MODE_EOS));

Definition at line 303 of file adc_112x.h.

STATIC INLINE void Chip_ADC_StartBurstSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Starts sequencer burst mode.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to start burst on
Returns
Nothing
Note
This function sets the BURST bit for the sequencer to force continuous conversion. Use Chip_ADC_StopBurstSequencer() to stop the ADC burst sequence.

Definition at line 352 of file adc_112x.h.

void Chip_ADC_StartCalibration ( LPC_ADC_T pADC)

Start ADC calibration.

Parameters
pADC: The base of ADC peripheral on the chip
Returns
Nothing
Note
Calibration is not done as part of Chip_ADC_Init(), but is required after the call to Chip_ADC_Init() or after returning from a power-down state.

Definition at line 143 of file adc_112x.c.

STATIC INLINE void Chip_ADC_StartSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Forces a sequencer trigger event (software trigger of ADC)

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to start
Returns
Nothing
Note
This function sets the START bit for the sequencer to force a single conversion sequence or a single step conversion.

Definition at line 338 of file adc_112x.h.

STATIC INLINE void Chip_ADC_StopBurstSequencer ( LPC_ADC_T pADC,
ADC_SEQ_IDX_T  seqIndex 
)

Stops sequencer burst mode.

Parameters
pADC: The base of ADC peripheral on the chip
seqIndex: Sequencer to stop burst on
Returns
Nothing

Definition at line 363 of file adc_112x.h.