LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
clock_112x.c
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1 /*
2  * @brief LPC11XX System clock control functions
3  *
4  * Copyright(C) NXP Semiconductors, 2012
5  * All rights reserved.
6  *
7  * Software that is described herein is for illustrative purposes only
8  * which provides customers with programming information regarding the
9  * LPC products. This software is supplied "AS IS" without any warranties of
10  * any kind, and NXP Semiconductors and its licensor disclaim any and
11  * all warranties, express or implied, including all implied warranties of
12  * merchantability, fitness for a particular purpose and non-infringement of
13  * intellectual property rights. NXP Semiconductors assumes no responsibility
14  * or liability for the use of the software, conveys no license or rights under any
15  * patent, copyright, mask work right, or any other intellectual property rights in
16  * or to any products. NXP Semiconductors reserves the right to make changes
17  * in the software without notification. NXP Semiconductors also makes no
18  * representation or warranty that such application will be suitable for the
19  * specified use without further testing or modification.
20  *
21  * Permission to use, copy, modify, and distribute this software and its
22  * documentation is hereby granted, under NXP Semiconductors' and its
23  * licensor's relevant copyrights in the software, without fee, provided that it
24  * is used in conjunction with NXP Semiconductors microcontrollers. This
25  * copyright, permission, and disclaimer notice must appear in all copies of
26  * this code.
27  */
28 
29 #include "chip.h"
30 
31 /*****************************************************************************
32  * Private types/enumerations/variables
33  ****************************************************************************/
34 
35 /* Inprecise clock rates for the watchdog oscillator */
36 STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
37  0, /* WDT_OSC_ILLEGAL */
38  600000, /* WDT_OSC_0_60 */
39  1050000, /* WDT_OSC_1_05 */
40  1400000, /* WDT_OSC_1_40 */
41  1750000, /* WDT_OSC_1_75 */
42  2100000, /* WDT_OSC_2_10 */
43  2400000, /* WDT_OSC_2_40 */
44  2700000, /* WDT_OSC_2_70 */
45  3000000, /* WDT_OSC_3_00 */
46  3250000, /* WDT_OSC_3_25 */
47  3500000, /* WDT_OSC_3_50 */
48  3750000, /* WDT_OSC_3_75 */
49  4000000, /* WDT_OSC_4_00 */
50  4200000, /* WDT_OSC_4_20 */
51  4400000, /* WDT_OSC_4_40 */
52  4600000 /* WDT_OSC_4_60 */
53 };
54 
55 /*****************************************************************************
56  * Public types/enumerations/variables
57  ****************************************************************************/
58 
59 /*****************************************************************************
60  * Private functions
61  ****************************************************************************/
62 
63 /* Compute a WDT or LFO rate */
64 STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
65 {
66  uint32_t div;
68 
69  /* Get WDT oscillator settings */
70  clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
71  div = reg & 0x1F;
72 
73  /* Compute clock rate and divided by divde value */
74  return wdtOSCRate[clk] / ((div + 1) << 1);
75 }
76 
77 /* Compute a PLL frequency */
78 STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
79 {
80  uint32_t msel = ((PLLReg & 0x1F) + 1);
81 
82  return inputRate * msel;
83 }
84 
85 /*****************************************************************************
86  * Public functions
87  ****************************************************************************/
88 
89 /* Set System PLL clock source */
91 {
92  LPC_SYSCON->SYSPLLCLKSEL = (uint32_t) src;
93  LPC_SYSCON->SYSPLLCLKUEN = 0;
94  LPC_SYSCON->SYSPLLCLKUEN = 1;
95 }
96 
97 /* Bypass System Oscillator and set oscillator frequency range */
98 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
99 {
100  uint32_t ctrl = 0;
101 
102  if (bypass) {
103  ctrl |= (1 << 0);
104  }
105  if (highfr) {
106  ctrl |= (1 << 1);
107  }
108 
109  LPC_SYSCON->SYSOSCCTRL = ctrl;
110 }
111 
112 /* Set main system clock source */
114 {
115  LPC_SYSCON->MAINCLKSEL = (uint32_t) src;
116  LPC_SYSCON->MAINCLKUEN = 0;
117  LPC_SYSCON->MAINCLKUEN = 1;
118 }
119 
120 /* Set WDT clock source and divider */
122 {
123  LPC_SYSCON->WDTCLKSEL = (uint32_t) src;
124  LPC_SYSCON->WDTCLKUEN = 0;
125  LPC_SYSCON->WDTCLKUEN = 1;
126  LPC_SYSCON->WDTCLKDIV = div;
127 }
128 
129 /* Set CLKOUT clock source and divider */
131 {
132  LPC_SYSCON->CLKOUTSEL = (uint32_t) src;
133  LPC_SYSCON->CLKOUTUEN = 0;
134  LPC_SYSCON->CLKOUTUEN = 1;
135  LPC_SYSCON->CLKOUTDIV = div;
136 }
137 
138 
139 /* Return estimated watchdog oscillator rate */
141 {
142  return Chip_Clock_GetWDTLFORate(LPC_SYSCON->WDTOSCCTRL);
143 }
144 
145 /* Return System PLL input clock rate */
147 {
148  uint32_t clkRate;
149 
150  switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3)) {
152  clkRate = Chip_Clock_GetIntOscRate();
153  break;
154 
156  clkRate = Chip_Clock_GetMainOscRate();
157  break;
158 
159  default:
160  clkRate = 0;
161  }
162 
163  return clkRate;
164 }
165 
166 /* Return System PLL output clock rate */
168 {
169  return Chip_Clock_GetPLLFreq(LPC_SYSCON->SYSPLLCTRL,
171 }
172 
173 /* Return main clock rate */
175 {
176  uint32_t clkRate = 0;
177 
178  switch ((CHIP_SYSCON_MAINCLKSRC_T) (LPC_SYSCON->MAINCLKSEL & 0x3)) {
180  clkRate = Chip_Clock_GetIntOscRate();
181  break;
182 
185  break;
186 
188  clkRate = Chip_Clock_GetWDTOSCRate();
189  break;
190 
193  break;
194  }
195 
196  return clkRate;
197 }
198 
199 /* Return system clock rate */
201 {
202  /* No point in checking for divide by 0 */
203  return Chip_Clock_GetMainClockRate() / LPC_SYSCON->SYSAHBCLKDIV;
204 }