LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
clock_112x.h
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1 /*
2  * @brief LPC11XX Clock control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CLOCK_1125_H_
33 #define __CLOCK_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
45 #define SYSCON_IRC_FREQ (12000000)
46 
54 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
55 {
56  LPC_SYSCON->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
57 }
58 
64 {
65  return (bool) ((LPC_SYSCON->SYSPLLSTAT & 1) != 0);
66 }
67 
71 typedef enum CHIP_SYSCON_PLLCLKSRC {
77 
86 
96 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
97 
101 typedef enum CHIP_WDTLFO_OSC {
119 
128 {
129  LPC_SYSCON->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
130 }
131 
135 typedef enum CHIP_SYSCON_MAINCLKSRC {
142 
151 
157 {
158  return (CHIP_SYSCON_MAINCLKSRC_T) (LPC_SYSCON->MAINCLKSEL);
159 }
160 
169 {
170  LPC_SYSCON->SYSAHBCLKDIV = div;
171 }
172 
176 typedef enum CHIP_SYSCON_CLOCK {
197 
204 {
205  LPC_SYSCON->SYSAHBCLKCTRL |= (1 << clk);
206 }
207 
214 {
215  LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << clk);
216 }
217 
226 {
227  LPC_SYSCON->SSP0CLKDIV = div;
228 }
229 
236 {
237  return LPC_SYSCON->SSP0CLKDIV;
238 }
239 
248 {
249  LPC_SYSCON->UART0CLKDIV = div;
250 }
251 
258 {
259  return LPC_SYSCON->UART0CLKDIV;
260 }
261 
270 {
271  LPC_SYSCON->SSP1CLKDIV = div;
272 }
273 
280 {
281  return LPC_SYSCON->SSP1CLKDIV;
282 }
283 
287 typedef enum CHIP_SYSCON_WDTCLKSRC {
292 
304 
308 typedef enum CHIP_SYSCON_CLKOUTSRC {
315 
327 
333 {
334  return OscRateIn;
335 }
336 
342 {
343  return SYSCON_IRC_FREQ;
344 }
345 
351 uint32_t Chip_Clock_GetWDTOSCRate(void);
352 
358 
364 
369 uint32_t Chip_Clock_GetMainClockRate(void);
370 
375 uint32_t Chip_Clock_GetSystemClockRate(void);
376 
381 #ifdef __cplusplus
382 }
383 #endif
384 
385 #endif /* __CLOCK_1125_H_ */