LPCOpen Platform for LPC112X microcontrollers
112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
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chip_112x
clock_112x.c
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/*
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* @brief LPC11XX System clock control functions
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*
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
chip.h
"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* Inprecise clock rates for the watchdog oscillator */
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STATIC
const
uint32_t
wdtOSCRate
[
WDTLFO_OSC_4_60
+ 1] = {
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0,
/* WDT_OSC_ILLEGAL */
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600000,
/* WDT_OSC_0_60 */
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1050000,
/* WDT_OSC_1_05 */
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1400000,
/* WDT_OSC_1_40 */
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1750000,
/* WDT_OSC_1_75 */
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2100000,
/* WDT_OSC_2_10 */
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2400000,
/* WDT_OSC_2_40 */
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2700000,
/* WDT_OSC_2_70 */
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3000000,
/* WDT_OSC_3_00 */
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3250000,
/* WDT_OSC_3_25 */
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3500000,
/* WDT_OSC_3_50 */
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3750000,
/* WDT_OSC_3_75 */
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4000000,
/* WDT_OSC_4_00 */
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4200000,
/* WDT_OSC_4_20 */
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4400000,
/* WDT_OSC_4_40 */
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4600000
/* WDT_OSC_4_60 */
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};
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/* Compute a WDT or LFO rate */
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STATIC
uint32_t
Chip_Clock_GetWDTLFORate
(uint32_t reg)
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{
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uint32_t div;
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CHIP_WDTLFO_OSC_T
clk;
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/* Get WDT oscillator settings */
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clk = (
CHIP_WDTLFO_OSC_T
) ((reg >> 5) & 0xF);
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div = reg & 0x1F;
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/* Compute clock rate and divided by divde value */
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return
wdtOSCRate
[clk] / ((div + 1) << 1);
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}
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/* Compute a PLL frequency */
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STATIC
uint32_t
Chip_Clock_GetPLLFreq
(uint32_t PLLReg, uint32_t inputRate)
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{
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uint32_t msel = ((PLLReg & 0x1F) + 1);
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return
inputRate * msel;
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Set System PLL clock source */
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void
Chip_Clock_SetSystemPLLSource
(
CHIP_SYSCON_PLLCLKSRC_T
src)
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{
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LPC_SYSCON
->SYSPLLCLKSEL = (uint32_t) src;
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LPC_SYSCON
->SYSPLLCLKUEN = 0;
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LPC_SYSCON
->SYSPLLCLKUEN = 1;
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}
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/* Bypass System Oscillator and set oscillator frequency range */
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void
Chip_Clock_SetPLLBypass
(
bool
bypass,
bool
highfr)
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{
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uint32_t ctrl = 0;
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if
(bypass) {
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ctrl |= (1 << 0);
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}
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if
(highfr) {
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ctrl |= (1 << 1);
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}
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LPC_SYSCON
->SYSOSCCTRL = ctrl;
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}
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/* Set main system clock source */
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void
Chip_Clock_SetMainClockSource
(
CHIP_SYSCON_MAINCLKSRC_T
src)
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{
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LPC_SYSCON
->MAINCLKSEL = (uint32_t) src;
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LPC_SYSCON
->MAINCLKUEN = 0;
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LPC_SYSCON
->MAINCLKUEN = 1;
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}
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/* Set WDT clock source and divider */
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void
Chip_Clock_SetWDTClockSource
(
CHIP_SYSCON_WDTCLKSRC_T
src, uint32_t div)
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{
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LPC_SYSCON
->WDTCLKSEL = (uint32_t) src;
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LPC_SYSCON
->WDTCLKUEN = 0;
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LPC_SYSCON
->WDTCLKUEN = 1;
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LPC_SYSCON
->WDTCLKDIV = div;
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}
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/* Set CLKOUT clock source and divider */
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void
Chip_Clock_SetCLKOUTSource
(
CHIP_SYSCON_CLKOUTSRC_T
src, uint32_t div)
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{
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LPC_SYSCON
->CLKOUTSEL = (uint32_t) src;
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LPC_SYSCON
->CLKOUTUEN = 0;
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LPC_SYSCON
->CLKOUTUEN = 1;
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LPC_SYSCON
->CLKOUTDIV = div;
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}
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/* Return estimated watchdog oscillator rate */
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uint32_t
Chip_Clock_GetWDTOSCRate
(
void
)
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{
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return
Chip_Clock_GetWDTLFORate
(
LPC_SYSCON
->WDTOSCCTRL);
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}
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/* Return System PLL input clock rate */
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uint32_t
Chip_Clock_GetSystemPLLInClockRate
(
void
)
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{
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uint32_t clkRate;
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switch
((
CHIP_SYSCON_PLLCLKSRC_T
) (
LPC_SYSCON
->SYSPLLCLKSEL & 0x3)) {
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case
SYSCON_PLLCLKSRC_IRC
:
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clkRate =
Chip_Clock_GetIntOscRate
();
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break
;
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case
SYSCON_PLLCLKSRC_MAINOSC
:
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clkRate =
Chip_Clock_GetMainOscRate
();
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break
;
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default
:
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clkRate = 0;
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}
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return
clkRate;
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}
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/* Return System PLL output clock rate */
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uint32_t
Chip_Clock_GetSystemPLLOutClockRate
(
void
)
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{
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return
Chip_Clock_GetPLLFreq
(
LPC_SYSCON
->SYSPLLCTRL,
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Chip_Clock_GetSystemPLLInClockRate
());
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}
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/* Return main clock rate */
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uint32_t
Chip_Clock_GetMainClockRate
(
void
)
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{
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uint32_t clkRate = 0;
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switch
((
CHIP_SYSCON_MAINCLKSRC_T
) (
LPC_SYSCON
->MAINCLKSEL & 0x3)) {
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case
SYSCON_MAINCLKSRC_IRC
:
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clkRate =
Chip_Clock_GetIntOscRate
();
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break
;
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case
SYSCON_MAINCLKSRC_PLLIN
:
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clkRate =
Chip_Clock_GetSystemPLLInClockRate
();
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break
;
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case
SYSCON_MAINCLKSRC_WDTOSC
:
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clkRate =
Chip_Clock_GetWDTOSCRate
();
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break
;
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case
SYSCON_MAINCLKSRC_PLLOUT
:
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clkRate =
Chip_Clock_GetSystemPLLOutClockRate
();
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break
;
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}
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return
clkRate;
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}
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/* Return system clock rate */
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uint32_t
Chip_Clock_GetSystemClockRate
(
void
)
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{
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/* No point in checking for divide by 0 */
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return
Chip_Clock_GetMainClockRate
() /
LPC_SYSCON
->SYSAHBCLKDIV;
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}
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