50 #define UDA_EVALM_CLK 0x00
51 #define UDA_BUS_CTRL 0x01
52 #define UDA_POWER_CTRL 0x02
53 #define UDA_ANALOG_CTRL 0x03
54 #define UDA_HPAMP_CTRL 0x04
55 #define UDA_MASTER_VOL_CTRL 0x10
56 #define UDA_MIXER_VOL_CTRL 0x11
57 #define UDA_MODE_CTRL 0x12
58 #define UDA_MUTE_CTRL 0x13
59 #define UDA_MIXER_FILTER_CTRL 0x14
60 #define UDA_DEC_VOL_CTRL 0x20
61 #define UDA_PGA_CTRL 0x21
62 #define UDA_ADC_CTRL 0x22
63 #define UDA_AGC_CTRL 0x23
64 #define UDA_TOTAL_REG 0x24
67 #define EVCLK_EV2 (1 << 15)
68 #define EVCLK_EV1 (1 << 14)
69 #define EVCLK_EV0 (1 << 13)
70 #define EVCLK_EN_ADC (1 << 11)
71 #define EVCLK_EN_DEC (1 << 10)
72 #define EVCLK_EN_DAC (1 << 9)
73 #define EVCLK_EN_INT (1 << 8)
74 #define EVCLK_ADC_CLK (1 << 5)
75 #define EVCLK_DAC_CLK (1 << 4)
76 #define EVCLK_SYS_DIV1 (1 << 3)
77 #define EVCLK_SYS_DIV0 (1 << 2)
78 #define EVCLK_PLL1 (1 << 1)
79 #define EVCLK_PLL0 (1 << 0)
82 #define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1)
83 #define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000
85 #define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
86 #define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000
87 #define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2)
89 #define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000
90 #define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000
91 #define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000
92 #define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2)
93 #define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000
95 #define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4
96 #define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000
97 #define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001
98 #define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000
100 #define UDA1380_REG_L3_DEFAULT_VALUE 0x0000
103 #define UDA1380_LINE_IN 0
104 #define UDA1380_MIC_IN_L (1 << 2)
105 #define UDA1380_MIC_IN_LR (3 << 2)
116 #define UDA1380_U8(val) (((val) >> 8) & 0xFF), ((val) & 0xFF)