LPCOpen SPIFI FLASH Library (LPCSPIFILIB)
Documentation for the LPCSPIFILIB library
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Macros | |
#define | SPIFI_CTRL_TO(t) ((t) << 0) |
SPIFI controller control register bit definitions. More... | |
#define | SPIFI_CTRL_CSHI(c) ((c) << 16) |
#define | SPIFI_CTRL_DATA_PREFETCH_DISABLE(d) ((d) << 21) |
#define | SPIFI_CTRL_INTEN(i) ((i) << 22) |
#define | SPIFI_CTRL_MODE3(m) ((m) << 23) |
#define | SPIFI_CTRL_PREFETCH_DISABLE(d) ((d) << 27) |
#define | SPIFI_CTRL_DUAL(d) ((d) << 28) |
#define | SPIFI_CTRL_RFCLK(m) ((m) << 29) |
#define | SPIFI_CTRL_FBCLK(m) ((m) << 30) |
#define | SPIFI_CTRL_DMAEN(m) ((m) << 31) |
#define | SPIFI_STAT_RESET (1 << 4) |
SPIFI controller status register bit definitions. More... | |
#define | SPIFI_STAT_INTRQ (1 << 5) |
#define | SPIFI_STAT_CMD (1 << 1) |
#define | SPIFI_STAT_MCINIT (1) |
#define | SPIFI_CMD_DATALEN(l) ((l) << 0) |
SPIFI controller command register bit definitions. More... | |
#define | SPIFI_CMD_POLLRS(p) ((p) << 14) |
#define | SPIFI_CMD_DOUT(d) ((d) << 15) |
#define | SPIFI_CMD_INTER(i) ((i) << 16) |
#define | SPIFI_CMD_FIELDFORM(p) ((p) << 19) |
#define | SPIFI_CMD_FRAMEFORM(f) ((f) << 21) |
#define | SPIFI_CMD_OPCODE(o) ((uint32_t) (o) << 24) |
Enumerations | |
enum | SPIFI_FRAMEFORM_T { SPIFI_FRAMEFORM_OP = 1, SPIFI_FRAMEFORM_OP_1ADDRESS = 2, SPIFI_FRAMEFORM_OP_2ADDRESS = 3, SPIFI_FRAMEFORM_OP_3ADDRESS = 4, SPIFI_FRAMEFORM_OP_4ADDRESS = 5, SPIFI_FRAMEFORM_NOOP_3ADDRESS = 6, SPIFI_FRAMEFORM_NOOP_4ADDRESS = 7 } |
frame form definitions | |
enum | SPIFI_FIELDFORM_T { SPIFI_FIELDFORM_ALL_SERIAL = 0, SPIFI_FIELDFORM_SERIAL_OPCODE_ADDRESS = 1, SPIFI_FIELDFORM_SERIAL_OPCODE = 2, SPIFI_FIELDFORM_NO_SERIAL = 3 } |
serial type definitions | |
Functions | |
static INLINE void | spifi_HW_SetCtrl (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t ctrl) |
Write SPIFI controller control register. More... | |
static INLINE uint32_t | spifi_HW_GetCtrl (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read SPIFI controller control register. More... | |
static INLINE void | spifi_HW_SetStat (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t stat) |
Write SPIFI controller status register. More... | |
static INLINE uint32_t | spifi_HW_GetStat (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read SPIFI controller status register. More... | |
static INLINE uint32_t | spifi_HW_GetCmd (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read SPIFI controller command register. More... | |
static INLINE void | spifi_HW_SetCmd (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd) |
Write SPIFI controller command register. More... | |
static INLINE void | spifi_HW_SetAddr (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t addr) |
Write SPIFI controller address register. More... | |
static INLINE uint8_t | spifi_HW_GetData8 (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read an 8-bit value from the controller data register. More... | |
static INLINE uint16_t | spifi_HW_GetData16 (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read an 16-bit value from the controller data register. More... | |
static INLINE uint32_t | spifi_HW_GetData32 (LPC_SPIFI_CHIPHW_T *pSpifi) |
Read an 32-bit value from the controller data register. More... | |
static INLINE void | spifi_HW_SetData8 (LPC_SPIFI_CHIPHW_T *pSpifi, uint8_t data) |
Write an 8-bit value from the controller data register. More... | |
static INLINE void | spifi_HW_SetData16 (LPC_SPIFI_CHIPHW_T *pSpifi, uint16_t data) |
Write an 16-bit value from the controller data register. More... | |
static INLINE void | spifi_HW_SetData32 (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t data) |
Write an 32-bit value from the controller data register. More... | |
static INLINE void | spifi_HW_SetIDATA (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t mode) |
Write IDATA register. More... | |
static INLINE void | spifi_HW_SetMEMCMD (LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd) |
Write MEMCMD register. More... | |
#define SPIFI_CMD_DATALEN | ( | l | ) | ((l) << 0) |
SPIFI controller command register bit definitions.
SPIFI bytes to send or receive
#define SPIFI_CMD_DOUT | ( | d | ) | ((d) << 15) |
SPIFI data direction is out
#define SPIFI_CMD_FIELDFORM | ( | p | ) | ((p) << 19) |
SPIFI 2 bit data/cmd mode control
#define SPIFI_CMD_FRAMEFORM | ( | f | ) | ((f) << 21) |
SPIFI op and adr field config
#define SPIFI_CMD_INTER | ( | i | ) | ((i) << 16) |
SPIFI intermediate bit length
#define SPIFI_CMD_OPCODE | ( | o | ) | ((uint32_t) (o) << 24) |
SPIFI 8-bit command code
#define SPIFI_CMD_POLLRS | ( | p | ) | ((p) << 14) |
SPIFI enable poll
#define SPIFI_CTRL_CSHI | ( | c | ) | ((c) << 16) |
SPIFI chip select minimum high time
#define SPIFI_CTRL_DATA_PREFETCH_DISABLE | ( | d | ) | ((d) << 21) |
SPIFI memMode prefetch enable
#define SPIFI_CTRL_DMAEN | ( | m | ) | ((m) << 31) |
SPIFI dma enable
#define SPIFI_CTRL_DUAL | ( | d | ) | ((d) << 28) |
SPIFI enable dual
#define SPIFI_CTRL_FBCLK | ( | m | ) | ((m) << 30) |
SPIFI feedback clock select
#define SPIFI_CTRL_INTEN | ( | i | ) | ((i) << 22) |
SPIFI cmdComplete irq enable
#define SPIFI_CTRL_MODE3 | ( | m | ) | ((m) << 23) |
SPIFI mode3 config
#define SPIFI_CTRL_PREFETCH_DISABLE | ( | d | ) | ((d) << 27) |
SPIFI cache prefetch enable
#define SPIFI_CTRL_RFCLK | ( | m | ) | ((m) << 29) |
SPIFI clock edge config
#define SPIFI_CTRL_TO | ( | t | ) | ((t) << 0) |
SPIFI controller control register bit definitions.
SPIFI timeout
#define SPIFI_STAT_CMD (1 << 1) |
SPIFI command in progress
#define SPIFI_STAT_INTRQ (1 << 5) |
SPIFI interrupt request
#define SPIFI_STAT_MCINIT (1) |
SPIFI MCINIT
#define SPIFI_STAT_RESET (1 << 4) |
SPIFI controller status register bit definitions.
SPIFI reset
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Read SPIFI controller command register.
pSpifi | : Base address of SPIFI controller |
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Read SPIFI controller control register.
pSpifi | : Base address of SPIFI controller |
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Read an 16-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
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Read an 32-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
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Read an 8-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
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Read SPIFI controller status register.
pSpifi | : Base address of SPIFI controller |
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Write SPIFI controller address register.
pSpifi | : Base address of SPIFI controller |
addr | : address (offset) to write |
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Write SPIFI controller command register.
pSpifi | : Base address of SPIFI controller |
cmd | : Command to write |
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Write SPIFI controller control register.
pSpifi | : Base address of SPIFI controller |
ctrl | : Control value to write |
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Write an 16-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
data | : 16-bit data value to write |
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Write an 32-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
data | : 32-bit data value to write |
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Write an 8-bit value from the controller data register.
pSpifi | : Base address of SPIFI controller |
data | : 8-bit data value to write |
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Write IDATA register.
pSpifi | : Base address of SPIFI controller |
mode | : value to write. Used to specify value used for intermediate data value when enabled. |
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Write MEMCMD register.
pSpifi | : Base address of SPIFI controller |
cmd | : Command value to write |
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Write SPIFI controller status register.
pSpifi | : Base address of SPIFI controller |
stat | : Status bits to write |