32 #ifndef __SPIFILIB_CHIPHW_H_
33 #define __SPIFILIB_CHIPHW_H_
44 #define INLINE __inline
60 volatile uint32_t
CMD;
81 #define SPIFI_CTRL_TO(t) ((t) << 0)
82 #define SPIFI_CTRL_CSHI(c) ((c) << 16)
83 #define SPIFI_CTRL_DATA_PREFETCH_DISABLE(d) ((d) << 21)
84 #define SPIFI_CTRL_INTEN(i) ((i) << 22)
85 #define SPIFI_CTRL_MODE3(m) ((m) << 23)
86 #define SPIFI_CTRL_PREFETCH_DISABLE(d) ((d) << 27)
87 #define SPIFI_CTRL_DUAL(d) ((d) << 28)
88 #define SPIFI_CTRL_RFCLK(m) ((m) << 29)
89 #define SPIFI_CTRL_FBCLK(m) ((m) << 30)
90 #define SPIFI_CTRL_DMAEN(m) ((m) << 31)
98 static INLINE void spifi_HW_SetCtrl(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t ctrl)
116 #define SPIFI_STAT_RESET (1 << 4)
117 #define SPIFI_STAT_INTRQ (1 << 5)
118 #define SPIFI_STAT_CMD (1 << 1)
119 #define SPIFI_STAT_MCINIT (1)
127 static INLINE void spifi_HW_SetStat(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t stat)
145 #define SPIFI_CMD_DATALEN(l) ((l) << 0)
146 #define SPIFI_CMD_POLLRS(p) ((p) << 14)
147 #define SPIFI_CMD_DOUT(d) ((d) << 15)
148 #define SPIFI_CMD_INTER(i) ((i) << 16)
149 #define SPIFI_CMD_FIELDFORM(p) ((p) << 19)
150 #define SPIFI_CMD_FRAMEFORM(f) ((f) << 21)
151 #define SPIFI_CMD_OPCODE(o) ((uint32_t) (o) << 24)
157 SPIFI_FRAMEFORM_OP = 1,
158 SPIFI_FRAMEFORM_OP_1ADDRESS = 2,
159 SPIFI_FRAMEFORM_OP_2ADDRESS = 3,
160 SPIFI_FRAMEFORM_OP_3ADDRESS = 4,
161 SPIFI_FRAMEFORM_OP_4ADDRESS = 5,
162 SPIFI_FRAMEFORM_NOOP_3ADDRESS = 6,
163 SPIFI_FRAMEFORM_NOOP_4ADDRESS = 7
170 SPIFI_FIELDFORM_ALL_SERIAL = 0,
171 SPIFI_FIELDFORM_SERIAL_OPCODE_ADDRESS = 1,
172 SPIFI_FIELDFORM_SERIAL_OPCODE = 2,
173 SPIFI_FIELDFORM_NO_SERIAL = 3
225 return pSpifi->
DAT16;
235 return pSpifi->
DAT32;
257 pSpifi->
DAT16 = data;
268 pSpifi->
DAT32 = data;
static INLINE void spifi_HW_SetData32(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t data)
Write an 32-bit value from the controller data register.
Definition: spifilib_chiphw.h:266
static INLINE void spifi_HW_WaitRESET(LPC_SPIFI_CHIPHW_T *pSpifi)
Wait for a RESET bit to clear.
Definition: spifilib_chiphw.h:328
#define SPIFI_STAT_CMD
Definition: spifilib_chiphw.h:118
static INLINE void spifi_HW_SetAddr(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t addr)
Write SPIFI controller address register.
Definition: spifilib_chiphw.h:203
static INLINE uint32_t spifi_HW_GetStat(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller status register.
Definition: spifilib_chiphw.h:137
volatile uint32_t CTRL
Definition: spifilib_chiphw.h:59
SPIFI_FIELDFORM_T
serial type definitions
Definition: spifilib_chiphw.h:169
static INLINE void spifi_HW_SetData8(LPC_SPIFI_CHIPHW_T *pSpifi, uint8_t data)
Write an 8-bit value from the controller data register.
Definition: spifilib_chiphw.h:244
static INLINE void spifi_HW_SetCmd(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
Write SPIFI controller command register.
Definition: spifilib_chiphw.h:192
volatile uint16_t DAT16
Definition: spifilib_chiphw.h:66
SPIFI_FRAMEFORM_T
frame form definitions
Definition: spifilib_chiphw.h:156
volatile uint32_t CACHELIMIT
Definition: spifilib_chiphw.h:63
static INLINE uint16_t spifi_HW_GetData16(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 16-bit value from the controller data register.
Definition: spifilib_chiphw.h:223
static INLINE uint8_t spifi_HW_GetData8(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 8-bit value from the controller data register.
Definition: spifilib_chiphw.h:213
static INLINE void spifi_HW_ResetController(LPC_SPIFI_CHIPHW_T *pSpifi)
Reset SPIFI controller.
Definition: spifilib_chiphw.h:307
#define SPIFI_STAT_RESET
SPIFI controller status register bit definitions.
Definition: spifilib_chiphw.h:116
static INLINE void spifi_HW_SetMEMCMD(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
Write MEMCMD register.
Definition: spifilib_chiphw.h:289
volatile uint32_t CMD
Definition: spifilib_chiphw.h:60
volatile uint32_t DAT32
Definition: spifilib_chiphw.h:67
volatile uint32_t DATINTM
Definition: spifilib_chiphw.h:62
volatile uint32_t STAT
Definition: spifilib_chiphw.h:71
SPIFI controller hardware register structure.
Definition: spifilib_chiphw.h:58
static INLINE void spifi_HW_SetIDATA(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t mode)
Write IDATA register.
Definition: spifilib_chiphw.h:278
volatile uint8_t DAT8
Definition: spifilib_chiphw.h:65
volatile uint32_t MEMCMD
Definition: spifilib_chiphw.h:70
static INLINE uint32_t spifi_HW_GetData32(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 32-bit value from the controller data register.
Definition: spifilib_chiphw.h:233
static INLINE void spifi_HW_SetData16(LPC_SPIFI_CHIPHW_T *pSpifi, uint16_t data)
Write an 16-bit value from the controller data register.
Definition: spifilib_chiphw.h:255
static INLINE uint32_t spifi_HW_GetCmd(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller command register.
Definition: spifilib_chiphw.h:181
volatile uint32_t ADDR
Definition: spifilib_chiphw.h:61
static INLINE void spifi_HW_WaitCMD(LPC_SPIFI_CHIPHW_T *pSpifi)
Wait for a command to complete.
Definition: spifilib_chiphw.h:318
struct LPC_SPIFI_CHIPHW LPC_SPIFI_CHIPHW_T
SPIFI controller hardware register structure.
static INLINE uint32_t spifi_HW_GetCtrl(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller control register.
Definition: spifilib_chiphw.h:108