LPCOpen SPIFI FLASH Library (LPCSPIFILIB)
Documentation for the LPCSPIFILIB library
spifilib_chiphw.h
1 /*
2  * @brief LPCSPIFILIB hardware definitions and functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2014
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licenser disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SPIFILIB_CHIPHW_H_
33 #define __SPIFILIB_CHIPHW_H_
34 
35 #include <stdint.h>
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /* Define for inline */
42 #ifndef INLINE
43 #ifdef __CC_ARM
44 #define INLINE __inline
45 #else
46 #define INLINE inline
47 #endif /* __CC_ARM */
48 #endif /* !INLINE */
49 
58 typedef struct LPC_SPIFI_CHIPHW {
59  volatile uint32_t CTRL;
60  volatile uint32_t CMD;
61  volatile uint32_t ADDR;
62  volatile uint32_t DATINTM;
63  volatile uint32_t CACHELIMIT;
64  union {
65  volatile uint8_t DAT8;
66  volatile uint16_t DAT16;
67  volatile uint32_t DAT32;
68  };
69 
70  volatile uint32_t MEMCMD;
71  volatile uint32_t STAT;
73 
81 #define SPIFI_CTRL_TO(t) ((t) << 0)
82 #define SPIFI_CTRL_CSHI(c) ((c) << 16)
83 #define SPIFI_CTRL_DATA_PREFETCH_DISABLE(d) ((d) << 21)
84 #define SPIFI_CTRL_INTEN(i) ((i) << 22)
85 #define SPIFI_CTRL_MODE3(m) ((m) << 23)
86 #define SPIFI_CTRL_PREFETCH_DISABLE(d) ((d) << 27)
87 #define SPIFI_CTRL_DUAL(d) ((d) << 28)
88 #define SPIFI_CTRL_RFCLK(m) ((m) << 29)
89 #define SPIFI_CTRL_FBCLK(m) ((m) << 30)
90 #define SPIFI_CTRL_DMAEN(m) ((m) << 31)
98 static INLINE void spifi_HW_SetCtrl(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t ctrl)
99 {
100  pSpifi->CTRL = ctrl;
101 }
102 
108 static INLINE uint32_t spifi_HW_GetCtrl(LPC_SPIFI_CHIPHW_T *pSpifi)
109 {
110  return pSpifi->CTRL;
111 }
112 
116 #define SPIFI_STAT_RESET (1 << 4)
117 #define SPIFI_STAT_INTRQ (1 << 5)
118 #define SPIFI_STAT_CMD (1 << 1)
119 #define SPIFI_STAT_MCINIT (1)
127 static INLINE void spifi_HW_SetStat(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t stat)
128 {
129  pSpifi->STAT = stat;
130 }
131 
137 static INLINE uint32_t spifi_HW_GetStat(LPC_SPIFI_CHIPHW_T *pSpifi)
138 {
139  return pSpifi->STAT;
140 }
141 
145 #define SPIFI_CMD_DATALEN(l) ((l) << 0)
146 #define SPIFI_CMD_POLLRS(p) ((p) << 14)
147 #define SPIFI_CMD_DOUT(d) ((d) << 15)
148 #define SPIFI_CMD_INTER(i) ((i) << 16)
149 #define SPIFI_CMD_FIELDFORM(p) ((p) << 19)
150 #define SPIFI_CMD_FRAMEFORM(f) ((f) << 21)
151 #define SPIFI_CMD_OPCODE(o) ((uint32_t) (o) << 24)
156 typedef enum {
157  SPIFI_FRAMEFORM_OP = 1,
158  SPIFI_FRAMEFORM_OP_1ADDRESS = 2,
159  SPIFI_FRAMEFORM_OP_2ADDRESS = 3,
160  SPIFI_FRAMEFORM_OP_3ADDRESS = 4,
161  SPIFI_FRAMEFORM_OP_4ADDRESS = 5,
162  SPIFI_FRAMEFORM_NOOP_3ADDRESS = 6,
163  SPIFI_FRAMEFORM_NOOP_4ADDRESS = 7
165 
169 typedef enum {
170  SPIFI_FIELDFORM_ALL_SERIAL = 0,
171  SPIFI_FIELDFORM_SERIAL_OPCODE_ADDRESS = 1,
172  SPIFI_FIELDFORM_SERIAL_OPCODE = 2,
173  SPIFI_FIELDFORM_NO_SERIAL = 3
175 
181 static INLINE uint32_t spifi_HW_GetCmd(LPC_SPIFI_CHIPHW_T *pSpifi)
182 {
183  return pSpifi->CMD;
184 }
185 
192 static INLINE void spifi_HW_SetCmd(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
193 {
194  pSpifi->CMD = cmd;
195 }
196 
203 static INLINE void spifi_HW_SetAddr(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t addr)
204 {
205  pSpifi->ADDR = addr;
206 }
207 
213 static INLINE uint8_t spifi_HW_GetData8(LPC_SPIFI_CHIPHW_T *pSpifi)
214 {
215  return pSpifi->DAT8;
216 }
217 
223 static INLINE uint16_t spifi_HW_GetData16(LPC_SPIFI_CHIPHW_T *pSpifi)
224 {
225  return pSpifi->DAT16;
226 }
227 
233 static INLINE uint32_t spifi_HW_GetData32(LPC_SPIFI_CHIPHW_T *pSpifi)
234 {
235  return pSpifi->DAT32;
236 }
237 
244 static INLINE void spifi_HW_SetData8(LPC_SPIFI_CHIPHW_T *pSpifi, uint8_t data)
245 {
246  pSpifi->DAT8 = data;
247 }
248 
255 static INLINE void spifi_HW_SetData16(LPC_SPIFI_CHIPHW_T *pSpifi, uint16_t data)
256 {
257  pSpifi->DAT16 = data;
258 }
259 
266 static INLINE void spifi_HW_SetData32(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t data)
267 {
268  pSpifi->DAT32 = data;
269 }
270 
278 static INLINE void spifi_HW_SetIDATA(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t mode)
279 {
280  pSpifi->DATINTM = mode;
281 }
282 
289 static INLINE void spifi_HW_SetMEMCMD(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
290 {
291  pSpifi->MEMCMD = cmd;
292 }
293 
307 static INLINE void spifi_HW_ResetController(LPC_SPIFI_CHIPHW_T *pSpifi)
308 {
309  pSpifi->STAT = SPIFI_STAT_RESET;
310  while ((pSpifi->STAT & SPIFI_STAT_RESET) != 0) {}
311 }
312 
318 static INLINE void spifi_HW_WaitCMD(LPC_SPIFI_CHIPHW_T *pSpifi)
319 {
320  while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_CMD) != 0) {}
321 }
322 
328 static INLINE void spifi_HW_WaitRESET(LPC_SPIFI_CHIPHW_T *pSpifi)
329 {
330  while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_RESET) != 0) {}
331 }
332 
341 #ifdef __cplusplus
342 }
343 #endif
344 
345 #endif /* __SPIFILIB_CHIPHW_H_ */
static INLINE void spifi_HW_SetData32(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t data)
Write an 32-bit value from the controller data register.
Definition: spifilib_chiphw.h:266
static INLINE void spifi_HW_WaitRESET(LPC_SPIFI_CHIPHW_T *pSpifi)
Wait for a RESET bit to clear.
Definition: spifilib_chiphw.h:328
#define SPIFI_STAT_CMD
Definition: spifilib_chiphw.h:118
static INLINE void spifi_HW_SetAddr(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t addr)
Write SPIFI controller address register.
Definition: spifilib_chiphw.h:203
static INLINE uint32_t spifi_HW_GetStat(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller status register.
Definition: spifilib_chiphw.h:137
volatile uint32_t CTRL
Definition: spifilib_chiphw.h:59
SPIFI_FIELDFORM_T
serial type definitions
Definition: spifilib_chiphw.h:169
static INLINE void spifi_HW_SetData8(LPC_SPIFI_CHIPHW_T *pSpifi, uint8_t data)
Write an 8-bit value from the controller data register.
Definition: spifilib_chiphw.h:244
static INLINE void spifi_HW_SetCmd(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
Write SPIFI controller command register.
Definition: spifilib_chiphw.h:192
volatile uint16_t DAT16
Definition: spifilib_chiphw.h:66
SPIFI_FRAMEFORM_T
frame form definitions
Definition: spifilib_chiphw.h:156
volatile uint32_t CACHELIMIT
Definition: spifilib_chiphw.h:63
static INLINE uint16_t spifi_HW_GetData16(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 16-bit value from the controller data register.
Definition: spifilib_chiphw.h:223
static INLINE uint8_t spifi_HW_GetData8(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 8-bit value from the controller data register.
Definition: spifilib_chiphw.h:213
static INLINE void spifi_HW_ResetController(LPC_SPIFI_CHIPHW_T *pSpifi)
Reset SPIFI controller.
Definition: spifilib_chiphw.h:307
#define SPIFI_STAT_RESET
SPIFI controller status register bit definitions.
Definition: spifilib_chiphw.h:116
static INLINE void spifi_HW_SetMEMCMD(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t cmd)
Write MEMCMD register.
Definition: spifilib_chiphw.h:289
volatile uint32_t CMD
Definition: spifilib_chiphw.h:60
volatile uint32_t DAT32
Definition: spifilib_chiphw.h:67
volatile uint32_t DATINTM
Definition: spifilib_chiphw.h:62
volatile uint32_t STAT
Definition: spifilib_chiphw.h:71
SPIFI controller hardware register structure.
Definition: spifilib_chiphw.h:58
static INLINE void spifi_HW_SetIDATA(LPC_SPIFI_CHIPHW_T *pSpifi, uint32_t mode)
Write IDATA register.
Definition: spifilib_chiphw.h:278
volatile uint8_t DAT8
Definition: spifilib_chiphw.h:65
volatile uint32_t MEMCMD
Definition: spifilib_chiphw.h:70
static INLINE uint32_t spifi_HW_GetData32(LPC_SPIFI_CHIPHW_T *pSpifi)
Read an 32-bit value from the controller data register.
Definition: spifilib_chiphw.h:233
static INLINE void spifi_HW_SetData16(LPC_SPIFI_CHIPHW_T *pSpifi, uint16_t data)
Write an 16-bit value from the controller data register.
Definition: spifilib_chiphw.h:255
static INLINE uint32_t spifi_HW_GetCmd(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller command register.
Definition: spifilib_chiphw.h:181
volatile uint32_t ADDR
Definition: spifilib_chiphw.h:61
static INLINE void spifi_HW_WaitCMD(LPC_SPIFI_CHIPHW_T *pSpifi)
Wait for a command to complete.
Definition: spifilib_chiphw.h:318
struct LPC_SPIFI_CHIPHW LPC_SPIFI_CHIPHW_T
SPIFI controller hardware register structure.
static INLINE uint32_t spifi_HW_GetCtrl(LPC_SPIFI_CHIPHW_T *pSpifi)
Read SPIFI controller control register.
Definition: spifilib_chiphw.h:108