**********************************************************************
*   MC68306 Assembly Header File                                     *
*                                                                    *
*   Developed by       : Motorola                                    *
*                        High Performance Embedded Systems Division  *
*                        Austin, TX                                  *
*                                                                    *
**********************************************************************

* System Registers

CSC0       EQU      $FFFFFFC0      ; Chip Select Configuration Register 0
CSC0H      EQU      $FFFFFFC0      ; Chip Select Configuration Register 0 (High Half)
CSC0L      EQU      $FFFFFFC2      ; Chip Select Configuration Register 0 (Low Half)
CSC1       EQU      $FFFFFFC4      ; Chip Select Configuration Register 1
CSC1H      EQU      $FFFFFFC4      ; Chip Select Configuration Register 1 (High Half)
CSC1L      EQU      $FFFFFFC6      ; Chip Select Configuration Register 1 (Low Half)
CSC2       EQU      $FFFFFFC8      ; Chip Select Configuration Register 2
CSC2H      EQU      $FFFFFFC8      ; Chip Select Configuration Register 2 (High Half)
CSC2L      EQU      $FFFFFFCA      ; Chip Select Configuration Register 2 (Low Half)
CSC3       EQU      $FFFFFFCC      ; Chip Select Configuration Register 3
CSC3H      EQU      $FFFFFFCC      ; Chip Select Configuration Register 3 (High Half)
CSC3L      EQU      $FFFFFFCE      ; Chip Select Configuration Register 3 (Low Half)
CSC4       EQU      $FFFFFFD0      ; Chip Select Configuration Register 4
CSC4H      EQU      $FFFFFFD0      ; Chip Select Configuration Register 4 (High Half)
CSC4L      EQU      $FFFFFFD2      ; Chip Select Configuration Register 4 (Low Half)
CSC5       EQU      $FFFFFFD4      ; Chip Select Configuration Register 5
CSC5H      EQU      $FFFFFFD4      ; Chip Select Configuration Register 5 (High Half)
CSC5L      EQU      $FFFFFFD6      ; Chip Select Configuration Register 5 (Low Half)
CSC6       EQU      $FFFFFFD8      ; Chip Select Configuration Register 6
CSC6H      EQU      $FFFFFFD8      ; Chip Select Configuration Register 6 (High Half)
CSC6L      EQU      $FFFFFFDA      ; Chip Select Configuration Register 6 (Low Half)
CSC7       EQU      $FFFFFFDC      ; Chip Select Configuration Register 7
CSC7H      EQU      $FFFFFFDC      ; Chip Select Configuration Register 7 (High Half)
CSC7L      EQU      $FFFFFFDE      ; Chip Select Configuration Register 7 (Low Half)
DBC0       EQU      $FFFFFFE0      ; DRAM Bank Configuration Register 0
DBC0H      EQU      $FFFFFFE0      ; DRAM Bank Configuration Register 0 (High Half)
DBC0L      EQU      $FFFFFFE2      ; DRAM Bank Configuration Register 0 (Low Half)
DBC1       EQU      $FFFFFFE4      ; DRAM Bank Configuration Register 1
DBC1H      EQU      $FFFFFFE4      ; DRAM Bank Configuration Register 1 (High Half)
DBC1L      EQU      $FFFFFFE6      ; DRAM Bank Configuration Register 1 (Low Half)
PADAT      EQU      $FFFFFFF0      ; Port A Data Register
PBDAT      EQU      $FFFFFFF1      ; Port B Data Register
PADDR      EQU      $FFFFFFF2      ; Port A Data Direction Register
PBDDR      EQU      $FFFFFFF3      ; Port B Data Direction Register
PAPR       EQU      $FFFFFFF4      ; Port A Pins Register
PBPR       EQU      $FFFFFFF5      ; Port B Pins Register
ISR        EQU      $FFFFFFF8      ; Interrupt Status Register
ICR        EQU      $FFFFFFFA      ; Interrupt Control Register
DREF       EQU      $FFFFFFFC      ; DRAM Refresh Register
BTPR       EQU      $FFFFFFFD      ; Bus Timeout Period Register
SYSR       EQU      $FFFFFFFE      ; System Register
TVR        EQU      $FFFFFFFF      ; Timer Vector Register

* Serial Module Registers

DUMR1A     EQU      $FFFFF7E1      ; Mode Register 1A
DUMR2A     EQU      $FFFFF7E1      ; Mode Register 2A
DUSRA      EQU      $FFFFF7E3      ; Status Register A
DUCSRA     EQU      $FFFFF7E3      ; Clock Select Register A
DUCRA      EQU      $FFFFF7E5      ; Command Register A
DURBA      EQU      $FFFFF7E7      ; Receiver Buffer A
DUTBA      EQU      $FFFFF7E7      ; Transmitter Buffer A
DUIPCR     EQU      $FFFFF7E9      ; Input Port Change Register
DUACR      EQU      $FFFFF7E9      ; Auxiliary Control Register
DUISR      EQU      $FFFFF7EB      ; Interrupt Status Register
DUIMR      EQU      $FFFFF7EB      ; Interrupt Mask Register
DUCUR      EQU      $FFFFF7ED      ; Current MSB of Counter
DUCLR      EQU      $FFFFF7ED      ; Counter/Timer Upper Register
DUCTUR     EQU      $FFFFF7EF      ; Current LSB of Counter
DUCTLR     EQU      $FFFFF7EF      ; Counter/Timer Lower Register
DUMR1B     EQU      $FFFFF7F1      ; Mode Register 1B
DUMR2B     EQU      $FFFFF7F1      ; Mode Register 2B
DUSRB      EQU      $FFFFF7F3      ; Status Register B
DUCSRB     EQU      $FFFFF7F3      ; Clock Select Register B
DUCRB      EQU      $FFFFF7F5      ; Command Register B
DURBB      EQU      $FFFFF7F7      ; Receiver Buffer B
DUTBB      EQU      $FFFFF7F7      ; Transmitter Buffer B
DUIVR      EQU      $FFFFF7F9      ; Interrupt Vector Register
DUIP       EQU      $FFFFF7FB      ; Input Port Register
DUOPCR     EQU      $FFFFF7FB      ; Output Port Configuration Register
STARTCC    EQU      $FFFFF7FD      ; Start Counter Command
STOPCC     EQU      $FFFFF7FF      ; Stop Counter Command


