PK OS ! trustzone_lab/secure_ns/.cproject
SDK_2.x_EVK-MIMXRT685
evkmimxrt685_secure_faults_ns
2.7.0
platform.drivers.common.MIMXRT685S;platform.drivers.reset.MIMXRT685S;platform.drivers.clock.MIMXRT685S;device.MIMXRT685S_CMSIS.MIMXRT685S;platform.Include_core_cm33.MIMXRT685S;platform.Include_common.MIMXRT685S;platform.Include_dsp.MIMXRT685S;platform.drivers.power.MIMXRT685S;utility.debug_console.MIMXRT685S;component.serial_manager.MIMXRT685S;component.lists.MIMXRT685S;platform.utilities.assert.MIMXRT685S;component.usart_adapter.MIMXRT685S;platform.drivers.flexcomm_usart.MIMXRT685S;platform.drivers.flexcomm.MIMXRT685S;platform.drivers.flash_config.MIMXRT685S;platform.drivers.flexspi.MIMXRT685S;platform.drivers.cache_cache64.MIMXRT685S;component.serial_manager_uart.MIMXRT685S;device.MIMXRT685S_startup.MIMXRT685S;platform.drivers.lpc_iopctl.MIMXRT685S;platform.drivers.lpc_gpio.MIMXRT685S;platform.utilities.misc_utilities.MIMXRT685S;evkmimxrt685_secure_faults_ns;
evkmimxrt685
MIMXRT685SFVKB
cm33
cm33_MIMXRT685S
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
<Properties property_3="NXP" property_4="MIMXRT685S" property_count="5" version="100300"/>
<infoList vendor="NXP">
<info chip="MIMXRT685S" name="MIMXRT685S">
<chip>
<name>MIMXRT685S</name>
<family>MIMXRT600</family>
<vendor>NXP</vendor>
<memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/>
<memory id="RAM" size="4608" type="RAM"/>
<memoryInstance derived_from="Flash" driver="MIMXRT600_FlexSPI_B_MXIC_OPI.cfx" edited="true" id="QSPI_FLASH" location="0x8100000" size="0x100000"/>
<memoryInstance derived_from="RAM" edited="true" id="SRAM" location="0x20180000" size="0x80000"/>
<memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x40140000" size="0x4000"/>
</chip>
<processor>
<name gcc_name="cortex-m33">Cortex-M33</name>
<family>Cortex-M</family>
</processor>
</info>
</infoList>
</TargetConfig>
PK y y PK OS 7 trustzone_lab/secure_ns/.settings/language.settings.xml
PK^ PK OS % trustzone_lab/secure_ns/board/board.c/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "board.h"
#include "fsl_clock.h"
#include "fsl_flexspi.h"
#include "fsl_cache.h"
#include "fsl_power.h"
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
#include "fsl_i2c.h"
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#if defined BOARD_USE_CODEC
#include "fsl_i3c.h"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
#define BOARD_IS_XIP_FLEXSPI() \
((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
(((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
/*******************************************************************************
* Variables
******************************************************************************/
static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base);
/*******************************************************************************
* Code
******************************************************************************/
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
uint32_t uartClkSrcFreq;
/* attach FRG0 clock to FLEXCOMM0 (debug console) */
CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
{
flexspi_transfer_t flashXfer;
status_t status;
/* Write data */
flashXfer.deviceAddress = regAddr;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Write;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = 3;
flashXfer.data = mrVal;
flashXfer.dataSize = 1;
status = FLEXSPI_TransferBlocking(base, &flashXfer);
return status;
}
static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
{
flexspi_transfer_t flashXfer;
status_t status;
/* Read data */
flashXfer.deviceAddress = regAddr;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Read;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = 2;
flashXfer.data = mrVal;
flashXfer.dataSize = 2;
status = FLEXSPI_TransferBlocking(base, &flashXfer);
return status;
}
static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base)
{
flexspi_transfer_t flashXfer;
status_t status;
/* Write data */
flashXfer.deviceAddress = 0x0U;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Command;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = 4;
status = FLEXSPI_TransferBlocking(base, &flashXfer);
if (status == kStatus_Success)
{
/* for loop of 50000 is about 1ms (@200 MHz CPU) */
for (uint32_t i = 2000000U; i > 0; i--)
{
__NOP();
}
}
return status;
}
/* Initialize psram. */
status_t BOARD_InitPsRam(void)
{
flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 396000000, /* 396MHZ SPI serial clock, DDR serial clock 198M */
.isSck2Enabled = false,
.flashSize = 0x2000, /* 64Mb/KByte */
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 5,
.CSHoldTime = 3,
.CSSetupTime = 3,
.dataValidTime = 1,
.columnspace = 0,
.enableWordAddress = false,
.AWRSeqIndex = 1,
.AWRSeqNumber = 1,
.ARDSeqIndex = 0,
.ARDSeqNumber = 1,
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,
.enableWriteMask = true,
};
uint32_t customLUT[64] = {
/* Read Data */
[0] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
[1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
kFLEXSPI_8PAD, 0x04),
/* Write Data */
[4] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
[5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_WRITE_DDR,
kFLEXSPI_8PAD, 0x04),
/* Read Register */
[8] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x40, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
[9] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
kFLEXSPI_8PAD, 0x04),
/* Write Register */
[12] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xC0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
[13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x08, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD,
0x00),
/* reset */
[16] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFF, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x03),
};
uint32_t mr0mr1[1];
uint32_t mr4mr8[1];
uint32_t mr0Val[1];
uint32_t mr4Val[1];
uint32_t mr8Val[1];
flexspi_config_t config;
cache64_config_t cacheCfg;
status_t status = kStatus_Success;
POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI_SRAM);
POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI_SRAM);
POWER_ApplyPD();
CLOCK_AttachClk(kAUX0_PLL_to_FLEXSPI_CLK);
CLOCK_SetClkDiv(kCLOCK_DivFlexspiClk, 1);
RESET_PeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
/* Explicitly enable FlexSPI clock for PSRAM loader case which need to set FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL. */
CLOCK_EnableClock(kCLOCK_Flexspi);
/* As cache depends on FlexSPI power and clock, cache must be initialized after FlexSPI power/clock is set */
CACHE64_GetDefaultConfig(&cacheCfg);
CACHE64_Init(CACHE64_POLSEL, &cacheCfg);
#if BOARD_ENABLE_PSRAM_CACHE
CACHE64_EnableCache(CACHE64);
#endif
/* Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);
/* Init FLEXSPI. */
config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableAHBCachable = true;
config.ahbConfig.enableReadAddressOpt = true;
for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
{
config.ahbConfig.buffer[i].bufferSize = 0;
}
/* FlexSPI has total 1KB RX buffer.
* Set DMA0 master to use AHB Rx Buffer0.
*/
config.ahbConfig.buffer[0].masterIndex = 4; /* DMA0 */
config.ahbConfig.buffer[0].bufferSize = 512; /* Allocate 512B bytes for DMA0 */
config.ahbConfig.buffer[0].enablePrefetch = true;
config.ahbConfig.buffer[0].priority = 0;
/* All other masters use last buffer with 512B bytes. */
config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 512;
config.enableCombination = true;
FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &deviceconfig, kFLEXSPI_PortA1);
/* Update LUT table. */
FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 0, customLUT, ARRAY_SIZE(customLUT));
/* Do software reset. */
FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
/* Reset hyper ram. */
status = flexspi_hyper_ram_reset(BOARD_FLEXSPI_PSRAM);
if (status != kStatus_Success)
{
return status;
}
status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0mr1);
if (status != kStatus_Success)
{
return status;
}
status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4mr8);
if (status != kStatus_Success)
{
return status;
}
/* Enable RBX, burst length set to 1K. - MR8 */
mr8Val[0] = (mr4mr8[0] & 0xFF00U) >> 8U;
mr8Val[0] = mr8Val[0] | 0x0F;
status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x8, mr8Val);
if (status != kStatus_Success)
{
return status;
}
/* Set LC code to 0x04(LC=7, maximum frequency 200M) - MR0. */
mr0Val[0] = mr0mr1[0] & 0x00FFU;
mr0Val[0] = (mr0Val[0] & ~0x3C) | (4 << 2U);
status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0Val);
if (status != kStatus_Success)
{
return status;
}
/* Set WLC code to 0x01(WLC=7, maximum frequency 200M) - MR4. */
mr4Val[0] = mr4mr8[0] & 0x00FFU;
mr4Val[0] = (mr4Val[0] & ~0xE0) | (1 << 5U);
status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4Val);
if (status != kStatus_Success)
{
return status;
}
return status;
}
void BOARD_DeinitXip(FLEXSPI_Type *base)
{
/* Wait until FLEXSPI is not busy */
while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
{
}
/* Disable module during the reset procedure */
base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
}
void BOARD_InitXip(FLEXSPI_Type *base)
{
uint32_t status;
uint32_t lastStatus;
uint32_t retry;
uint32_t mask = 0;
/* Enable FLEXSPI module */
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
{
}
/* Need to wait DLL locked if DLL enabled */
if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
{
lastStatus = base->STS2;
retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
/* Flash on port A */
if ((base->FLSHCR0[0] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
(base->FLSHCR0[1] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
{
mask |= FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK;
}
/* Flash on port B */
if ((base->FLSHCR0[2] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
(base->FLSHCR0[3] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
{
mask |= FLEXSPI_STS2_BREFLOCK_MASK | FLEXSPI_STS2_BSLVLOCK_MASK;
}
/* Wait slave delay line locked and slave reference delay line locked. */
do
{
status = base->STS2;
if ((status & mask) == mask)
{
/* Locked */
retry = 100;
break;
}
else if (status == lastStatus)
{
/* Same delay cell number in calibration */
retry--;
}
else
{
retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
lastStatus = status;
}
} while (retry > 0);
/* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
for (; retry > 0U; retry--)
{
__NOP();
}
}
}
/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
{
if (CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src) ||
(CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1))
{
if (BOARD_IS_XIP_FLEXSPI())
{
BOARD_DeinitXip(FLEXSPI);
}
/* Disable clock before changing clock source */
CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI_OTFAD_CLK_MASK;
/* Update flexspi clock. */
CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
{
}
/* Enable FLEXSPI clock again */
CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK;
if (BOARD_IS_XIP_FLEXSPI())
{
BOARD_InitXip(FLEXSPI);
}
}
}
/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
* updating in case XIP(execute code on FLEXSPI memory.) */
void BOARD_FlexspiClockSafeConfig(void)
{
/* Move FLEXSPI clock source from main clock to FFRO to avoid instruction/data fetch issue in XIP when
* updating PLL and main clock.
*/
BOARD_SetFlexspiClock(3U, 1);
}
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
{
i2c_master_config_t i2cConfig = {0};
I2C_MasterGetDefaultConfig(&i2cConfig);
I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
}
status_t BOARD_I2C_Send(I2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
i2c_master_transfer_t masterXfer;
/* Prepare transfer structure. */
masterXfer.slaveAddress = deviceAddress;
masterXfer.direction = kI2C_Write;
masterXfer.subaddress = subAddress;
masterXfer.subaddressSize = subaddressSize;
masterXfer.data = txBuff;
masterXfer.dataSize = txBuffSize;
masterXfer.flags = kI2C_TransferDefaultFlag;
return I2C_MasterTransferBlocking(base, &masterXfer);
}
status_t BOARD_I2C_Receive(I2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
i2c_master_transfer_t masterXfer;
/* Prepare transfer structure. */
masterXfer.slaveAddress = deviceAddress;
masterXfer.subaddress = subAddress;
masterXfer.subaddressSize = subaddressSize;
masterXfer.data = rxBuff;
masterXfer.dataSize = rxBuffSize;
masterXfer.direction = kI2C_Read;
masterXfer.flags = kI2C_TransferDefaultFlag;
return I2C_MasterTransferBlocking(base, &masterXfer);
}
#endif
#if defined BOARD_USE_CODEC
void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz)
{
i3c_master_config_t i3cConfig;
I3C_MasterGetDefaultConfig(&i3cConfig);
I3C_MasterInit(base, &i3cConfig, clkSrc_Hz);
}
status_t BOARD_I3C_Send(I3C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
i3c_master_transfer_t masterXfer;
/* Prepare transfer structure. */
masterXfer.slaveAddress = deviceAddress;
masterXfer.direction = kI3C_Write;
masterXfer.busType = kI3C_TypeI2C;
masterXfer.subaddress = subAddress;
masterXfer.subaddressSize = subaddressSize;
masterXfer.data = txBuff;
masterXfer.dataSize = txBuffSize;
masterXfer.flags = kI3C_TransferDefaultFlag;
return I3C_MasterTransferBlocking(base, &masterXfer);
}
status_t BOARD_I3C_Receive(I3C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
i3c_master_transfer_t masterXfer;
/* Prepare transfer structure. */
masterXfer.slaveAddress = deviceAddress;
masterXfer.subaddress = subAddress;
masterXfer.subaddressSize = subaddressSize;
masterXfer.data = rxBuff;
masterXfer.dataSize = rxBuffSize;
masterXfer.direction = kI3C_Read;
masterXfer.busType = kI3C_TypeI2C;
masterXfer.flags = kI3C_TransferDefaultFlag;
return I3C_MasterTransferBlocking(base, &masterXfer);
}
void BOARD_Codec_I2C_Init(void)
{
#if BOARD_I3C_CODEC
BOARD_I3C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
#else
BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
#endif
}
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
#if BOARD_I3C_CODEC
return BOARD_I3C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
#else
return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
#endif
txBuffSize);
}
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
#if BOARD_I3C_CODEC
return BOARD_I3C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
#else
return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
#endif
}
#endif
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_PMIC_I2C_Init(void)
{
BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
}
status_t BOARD_PMIC_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_PMIC_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
void BOARD_Accel_I2C_Init(void)
{
BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
}
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
{
uint8_t data = (uint8_t)txBuff;
return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
}
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
}
#endif /* SDK_I2C_BASED_COMPONENT_USED */
PKLO O PK OS % trustzone_lab/secure_ns/board/board.h/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "clock_config.h"
#include "fsl_common.h"
#include "fsl_reset.h"
#include "fsl_gpio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "MIMXRT685-EVK"
#define BOARD_I3C_CODEC (1)
/*! @brief The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
#define BOARD_DEBUG_UART_INSTANCE 0U
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(0U)
#define BOARD_DEBUG_UART_FRG_CLK \
(&(const clock_frg_clk_config_t){0, kCLOCK_FrgPllDiv, 255, 0}) /*!< Select FRG0 mux as frg_pll */
#define BOARD_DEBUG_UART_CLK_ATTACH kFRG_to_FLEXCOMM0
#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
#define BOARD_UART_IRQ FLEXCOMM0_IRQn
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE 115200
#endif /* BOARD_DEBUG_UART_BAUDRATE */
#define BOARD_FLEXSPI_PSRAM FLEXSPI
#ifndef BOARD_ENABLE_PSRAM_CACHE
#define BOARD_ENABLE_PSRAM_CACHE 1
#endif
#if BOARD_I3C_CODEC
#define BOARD_CODEC_I2C_BASEADDR I3C
#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetI3cClkFreq()
#define BOARD_CODEC_I2C_INSTANCE 0
#else
#define BOARD_CODEC_I2C_BASEADDR I2C4
#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetFlexCommClkFreq(4U)
#define BOARD_CODEC_I2C_INSTANCE 4
#endif
#define BOARD_PMIC_I2C_BASEADDR I2C15
#define BOARD_PMIC_I2C_CLOCK_FREQ CLOCK_GetFlexCommClkFreq(15U)
#define BOARD_ACCEL_I2C_BASEADDR I2C2
#define BOARD_ACCEL_I2C_ADDR 0x1E
#define BOARD_ACCEL_I2C_CLOCK_FREQ CLOCK_GetFlexCommClkFreq(2U)
/* Board led color mapping */
#define LOGIC_LED_ON 1U
#define LOGIC_LED_OFF 0U
#ifndef BOARD_LED_RED_GPIO
#define BOARD_LED_RED_GPIO GPIO
#endif
#define BOARD_LED_RED_GPIO_PORT 0U
#ifndef BOARD_LED_RED_GPIO_PIN
#define BOARD_LED_RED_GPIO_PIN 31U
#endif
#ifndef BOARD_LED_GREEN_GPIO
#define BOARD_LED_GREEN_GPIO GPIO
#endif
#define BOARD_LED_GREEN_GPIO_PORT 0U
#ifndef BOARD_LED_GREEN_GPIO_PIN
#define BOARD_LED_GREEN_GPIO_PIN 14U
#endif
#ifndef BOARD_LED_BLUE_GPIO
#define BOARD_LED_BLUE_GPIO GPIO
#endif
#define BOARD_LED_BLUE_GPIO_PORT 0U
#ifndef BOARD_LED_BLUE_GPIO_PIN
#define BOARD_LED_BLUE_GPIO_PIN 26U
#endif
#define LED_RED_INIT(output) \
GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */
#define LED_RED_ON() \
GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
#define LED_RED_OFF() \
GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
#define LED_RED_TOGGLE() \
GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
#define LED_GREEN_INIT(output) \
GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */
#define LED_GREEN_ON() \
GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
#define LED_GREEN_OFF() \
GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
#define LED_GREEN_TOGGLE() \
GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
#define LED_BLUE_INIT(output) \
GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
#define LED_BLUE_ON() \
GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
#define LED_BLUE_OFF() \
GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
#define LED_BLUE_TOGGLE() \
GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
/* Board SW PIN */
#ifndef BOARD_SW1_GPIO
#define BOARD_SW1_GPIO GPIO
#endif
#define BOARD_SW1_GPIO_PORT 1U
#ifndef BOARD_SW1_GPIO_PIN
#define BOARD_SW1_GPIO_PIN 1U
#endif
#ifndef BOARD_SW2_GPIO
#define BOARD_SW2_GPIO GPIO
#endif
#define BOARD_SW2_GPIO_PORT 0U
#ifndef BOARD_SW2_GPIO_PIN
#define BOARD_SW2_GPIO_PIN 10U
#endif
/* USDHC configuration */
#define BOARD_SD_SUPPORT_180V (1)
#define BOARD_USDHC_CD_GPIO_BASE GPIO
#define BOARD_USDHC_CD_GPIO_PORT (2)
#define BOARD_USDHC_CD_GPIO_PIN (9)
#define BOARD_SD_POWER_RESET_GPIO (GPIO)
#define BOARD_SD_POWER_RESET_GPIO_PORT (2)
#define BOARD_SD_POWER_RESET_GPIO_PIN (10)
/* Card detect handled by uSDHC, no GPIO interrupt */
#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
#define BOARD_USDHC_CD_PORT_IRQ USDHC0_IRQn
#define BOARD_USDHC_CD_STATUS() 0
#define BOARD_USDHC_CD_INTERRUPT_STATUS() 0
#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag)
#define BOARD_USDHC_CD_GPIO_INIT()
#define BOARD_HAS_SDCARD (1U)
#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
{ \
GPIO_PortInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PORT); \
GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PORT, BOARD_SD_POWER_RESET_GPIO_PIN, \
&(gpio_pin_config_t){kGPIO_DigitalOutput, 0}); \
}
#define BOARD_MMC_SUPPORT_8BIT_BUS 0
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
(state ? \
GPIO_PortSet(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PORT, 1 << BOARD_SD_POWER_RESET_GPIO_PIN) : \
GPIO_PortClear(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PORT, \
1 << BOARD_SD_POWER_RESET_GPIO_PIN))
#define BOARD_USDHC0_BASEADDR USDHC0
#define BOARD_USDHC0_CLK_FREQ CLOCK_GetSdioClkFreq(0)
#define BOARD_USDHC_SWITCH_VOLTAGE_FUNCTION 1U
/* GT202 */
#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO
#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO
#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput
#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput
#define BOARD_INITGT202SHIELD_PWRON_PORT 1
#define BOARD_INITGT202SHIELD_IRQ_PORT 1
#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 9
#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 8
/* Silex2401 */
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 0
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 28
#define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
#define BOARD_SD_HOST_IRQ USDHC0_IRQn
#define BOARD_SD_Pin_Config(speed, strength)
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#define BOARD_FLASH_SIZE (0x4000000U)
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
void BOARD_InitDebugConsole(void);
status_t BOARD_InitPsRam(void);
void BOARD_FlexspiClockSafeConfig(void);
AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider));
AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitXip(FLEXSPI_Type *base));
AT_QUICKACCESS_SECTION_CODE(void BOARD_InitXip(FLEXSPI_Type *base));
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_I2C_Send(I2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_I2C_Receive(I2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
#endif
#if defined BOARD_USE_CODEC
void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_I3C_Send(I3C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_I3C_Receive(I3C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
void BOARD_Codec_I2C_Init(void);
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_PMIC_I2C_Init(void);
status_t BOARD_PMIC_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_PMIC_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Accel_I2C_Init(void);
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */
PKX)ef
0
0 PK OS , trustzone_lab/secure_ns/board/clock_config.c/*
* Copyright 2019 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to set up clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up all selectors to provide selected clocks.
*
* 3. Set up all dividers.
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
processor: MIMXRT685S
package_id: MIMXRT685SFVKB
mcu_data: ksdk2_0
processor_version: 0.0.3
board: MIMXRT685-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_power.h"
#include "fsl_clock.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_FlexspiClockSafeConfig
* Description : FLEXSPI clock source safe configuration weak function.
* Called before clock source(Such as PLL, Main clock) configuration.
* Note : Users need override this function to change FLEXSPI clock source to stable source when executing
* code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock
*source to an stable clock to avoid instruction/data fetch issue during clock updating.
*END**************************************************************************/
__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
{
}
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_SetFlexspiClock
* Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
* To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
* After the clock is changed and stable, move back to run on FLEXSPI.
* Param src : FLEXSPI clock source.
* Param divider : FLEXSPI clock divider.
*END**************************************************************************/
__attribute__((weak)) void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
{
CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
{
}
}
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: FLEXSPI_clock.outFreq, value: 1900.8/19 MHz}
- {id: LPOSC1M_clock.outFreq, value: 1 MHz}
- {id: OSTIMER_clock.outFreq, value: 1 MHz}
- {id: System_clock.outFreq, value: 4752/19 MHz}
- {id: TRACE_clock.outFreq, value: 4752/19 MHz}
- {id: WAKE_32K_clock.outFreq, value: 31.25 kHz}
settings:
- {id: AUDIOPLL0_PFD0_CLK_GATE, value: Enabled}
- {id: PFC0DIV_HALT, value: Enable}
- {id: PLL0_PFD0_CLK_GATE, value: Enabled}
- {id: PLL0_PFD2_CLK_GATE, value: Enabled}
- {id: SYSCON.AUDIOPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
- {id: SYSCON.AUDIOPLL0_PFD0_DIV.scale, value: '26', locked: true}
- {id: SYSCON.AUDIOPLLCLKDIV.scale, value: '15', locked: true}
- {id: SYSCON.AUDIO_PLL0_PFD0_MUL.scale, value: '18', locked: true}
- {id: SYSCON.FLEXSPIFCLKDIV.scale, value: '5', locked: true}
- {id: SYSCON.FLEXSPIFCLKSEL.sel, value: SYSCON.MAINPLLCLKDIV}
- {id: SYSCON.FRGPLLCLKDIV.scale, value: '12', locked: true}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.MAINPLLCLKDIV}
- {id: SYSCON.PFC0DIV.scale, value: '2', locked: true}
- {id: SYSCON.PFC1DIV.scale, value: '1', locked: true}
- {id: SYSCON.PLL0.denom, value: '1'}
- {id: SYSCON.PLL0.div, value: '22', locked: true}
- {id: SYSCON.PLL0.num, value: '0'}
- {id: SYSCON.PLL0_PFD0_DIV.scale, value: '19', locked: true}
- {id: SYSCON.PLL0_PFD0_MUL.scale, value: '18', locked: true}
- {id: SYSCON.PLL0_PFD2_DIV.scale, value: '24', locked: true}
- {id: SYSCON.PLL0_PFD2_MUL.scale, value: '18', locked: true}
- {id: SYSCON.PLL1.denom, value: '27000', locked: true}
- {id: SYSCON.PLL1.div, value: '22'}
- {id: SYSCON.PLL1.num, value: '5040', locked: true}
- {id: SYSCON.SYSCPUAHBCLKDIV.scale, value: '2'}
- {id: SYSCON.SYSPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
- {id: SYSCTL_PDRUNCFG_AUDIOPLL_CFG, value: 'No'}
- {id: SYSCTL_PDRUNCFG_SYSPLL_CFG, value: 'No'}
- {id: SYSCTL_PDRUNCFG_SYSXTAL_CFG, value: Power_up}
- {id: XTAL_LP_Enable, value: LowPowerMode}
sources:
- {id: SYSCON.XTAL.outFreq, value: 24 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN = {
.sys_pll_src = kCLOCK_SysPllXtalIn, /* OSC clock */
.numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider isnull */
.denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider isnull */
.sys_pll_mult = kCLOCK_SysPllMult22 /* Divide by 22 */
};
const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
.audio_pll_src = kCLOCK_AudioPllXtalIn, /* OSC clock */
.numerator = 5040, /* Numerator of the SYSPLL0 fractional loop divider isnull */
.denominator = 27000, /* Denominator of the SYSPLL0 fractional loop divider isnull */
.audio_pll_mult = kCLOCK_AudioPllMult22 /* Divide by 22 */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Configure LPOSC clock*/
POWER_DisablePD(kPDRUNCFG_PD_LPOSC); /* Power on LPOSC (1MHz) */
/* Configure FFRO clock */
POWER_DisablePD(kPDRUNCFG_PD_FFRO); /* Power on FFRO (48/60MHz) */
CLOCK_EnableFfroClk(kCLOCK_Ffro48M); /* Enable FFRO clock*/
/* Configure SFRO clock */
POWER_DisablePD(kPDRUNCFG_PD_SFRO); /* Power on SFRO (16MHz) */
CLOCK_EnableSfroClk(); /* Wait until SFRO stable */
/* Call function BOARD_FlexspiClockSafeConfig() to move FLEXSPI clock to a stable clock source to avoid
instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */
BOARD_FlexspiClockSafeConfig();
/* Let CPU run on ffro for safe switching */
CLOCK_AttachClk(kFFRO_to_MAIN_CLK);
/* Configure SYSOSC clock source */
POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); /* Power on SYSXTAL */
POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); /* Updated XTAL oscillator settling time */
CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); /* Sets external XTAL OSC freq */
/* Configure SysPLL0 clock source */
CLOCK_InitSysPll(&g_sysPllConfig_BOARD_BootClockRUN);
CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); /* Enable MAIN PLL clock */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Enable AUX0 PLL clock */
/* Configure Audio PLL clock source */
CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN);
CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); /* Enable Audio PLL clock */
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */
/* Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); /* Switch MAIN_CLK to MAIN_PLL */
/* Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */
CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */
CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); /* Set FRGPLLCLKDIV divider to value 12 */
/* Call weak function BOARD_SetFlexspiClock() to set user configured clock source/divider for FLEXSPI. */
BOARD_SetFlexspiClock(1U, 5U);
/*< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
PKǿ7&