//PF7100 - OTP Editor
//file generated on Wed Jan 4 13:03:34 2023
//Device Type:PF7100-QM
//OTP ID:A5
//Customer:NXP
//Part Number:SPF7100BVMA5ES

SET_DPIN:PF7100:PWRON:low
SET_DPIN:PF7100:WDI:low
SET_DPIN:PF7100:TBBEN:high

//MAIN_OTP
SET_REG:PF7100:OTP_MIRROR:OTP_FSOB_SELECT:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_I2C:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL1:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL2:0x05
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF7100:OTP_MIRROR:OTP_SW_RAMP:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_WD_CONFIG:0x30
SET_REG:PF7100:OTP_MIRROR:OTP_WD_EXPIRE:0x07
SET_REG:PF7100:OTP_MIRROR:OTP_WD_COUNTER:0xaf
SET_REG:PF7100:OTP_MIRROR:OTP_FAULT_COUNTER:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_FAULT_TIMERS:0x0f
SET_REG:PF7100:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_PWRDN_DLY2:0x80
SET_REG:PF7100:OTP_MIRROR:OTP_PWRUP_CTRL:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x09
SET_REG:PF7100:OTP_MIRROR:OTP_PGOOD_PWRUP:0x09
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_VOLT:0x50
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_PWRUP:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_CONFIG2:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_VOLT:0xb1
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_PWRUP:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_CONFIG2:0x0a
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_VOLT:0xb1
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_PWRUP:0x01
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_CONFIG2:0x12
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_VOLT:0xb1
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_PWRUP:0x06
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_CONFIG2:0x1a
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_VOLT:0x0d
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_PWRUP:0x06
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_CONFIG1:0xd3
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_CONFIG2:0x3a
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_VOLT:0x51
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_PWRUP:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_CONFIG:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_VOLT:0x57
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_PWRUP:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_CONFIG:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_ILIM_BYPASS1:0x4f
SET_REG:PF7100:OTP_MIRROR:OTP_ILIM_BYPASS2:0x03
SET_REG:PF7100:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_PROG_IDL:0x05
SET_REG:PF7100:OTP_MIRROR:OTP_DEBUG1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP1:0x24
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP2:0x24
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP3:0x00

//SET CRC VALUES
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA5
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA4

SET_DPIN:PF7100:TBBEN:low
SET_DPIN:PF7100:STANDBY:low
SET_DPIN:PF7100:PWRON:high

//Rev,A
