//Device Type:PF7100-B   OTP ID:BH
//Date: 20/5/2021
//Customer:Horizon Robotics

SET_DPIN:PF7100:PWRON:low
SET_DPIN:PF7100:WDI:low
SET_DPIN:PF7100:TBBEN:high
SET_DPIN:PF7100:USBEN:high
SET_DPIN:PF7100:BSTEN:high
SET_DPIN:PF7100:VDDOTPEN:high


//MAIN_OTP
SET_REG:PF7100:OTP_MIRROR:OTP_FSOB_SELECT:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_I2C:0x01
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL1:0x08
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL2:0x1d
SET_REG:PF7100:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF7100:OTP_MIRROR:OTP_SW_RAMP:0xaa
SET_REG:PF7100:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_WD_CONFIG:0x30
SET_REG:PF7100:OTP_MIRROR:OTP_WD_EXPIRE:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_WD_COUNTER:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_FAULT_COUNTER:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_FAULT_TIMERS:0x0f
SET_REG:PF7100:OTP_MIRROR:OTP_PWRDN_DLY1:0xa0
SET_REG:PF7100:OTP_MIRROR:OTP_PWRDN_DLY2:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_PWRUP_CTRL:0x7f
SET_REG:PF7100:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x17
SET_REG:PF7100:OTP_MIRROR:OTP_PGOOD_PWRUP:0x08
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_VOLT:0x70
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_PWRUP:0x05
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_CONFIG1:0x57
SET_REG:PF7100:OTP_MIRROR:OTP_SW1_CONFIG2:0x03
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_VOLT:0x70
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_PWRUP:0x05
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_CONFIG1:0x57
SET_REG:PF7100:OTP_MIRROR:OTP_SW2_CONFIG2:0x0b
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_VOLT:0x40
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_PWRUP:0x07
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW3_CONFIG2:0x13
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_VOLT:0x40
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_PWRUP:0x07
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_CONFIG1:0x53
SET_REG:PF7100:OTP_MIRROR:OTP_SW4_CONFIG2:0x1b
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_VOLT:0x08
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_PWRUP:0x02
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_CONFIG1:0x5f
SET_REG:PF7100:OTP_MIRROR:OTP_SW5_CONFIG2:0x23
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_VOLT:0x57
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_PWRUP:0x04
SET_REG:PF7100:OTP_MIRROR:OTP_LDO1_CONFIG:0x86
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_VOLT:0x57
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_PWRUP:0x07
SET_REG:PF7100:OTP_MIRROR:OTP_LDO2_CONFIG:0x16
SET_REG:PF7100:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_ILIM_BYPASS2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_PROG_IDH:0x01
SET_REG:PF7100:OTP_MIRROR:OTP_PROG_IDL:0x11
SET_REG:PF7100:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP1:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP2:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_LSB:0x00
SET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_MSB:0x00
// CONFIGURE OTP CONTROLLER
SET_REG:PF7100:OTP_PAGE2:FCMD:0x80
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF7100:OTP_PAGE2:FDATA:0xAC
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA9
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x02
SET_REG:PF7100:OTP_PAGE2:FDATA:0xDC
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA9
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x08
SET_REG:PF7100:OTP_PAGE2:FDATA:0x38
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA9
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x09
SET_REG:PF7100:OTP_PAGE2:FDATA:0xDC
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA9
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x0C
SET_REG:PF7100:OTP_PAGE2:FDATA:0xD2
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA9

SET_REG:PF7100:OTP_PAGE2:MAX_PGM_TRIES:0x08
SET_REG:PF7100:OTP_PAGE2:MRR_SVDR_IN:0x13
SET_REG:PF7100:OTP_PAGE2:MR_TEST_H:0x00
SET_REG:PF7100:OTP_PAGE2:MR_TEST_L:0x02
SET_REG:PF7100:OTP_PAGE2:MREF_TEST_H:0x00
SET_REG:PF7100:OTP_PAGE2:MREF_TEST_L:0x00
SET_REG:PF7100:OTP_PAGE2:PULSE_DUR_1:0xBB
SET_REG:PF7100:OTP_PAGE2:PULSE_DUR_2:0x08
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF7100:OTP_PAGE2:FADDR_STOP:0x48

//SET CRC Valules
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA5
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA4
GET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_MSB

// START FUSE PROGRAMMING
SET_REG:PF7100:OTP_PAGE2:FCMD:0x96
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS

// BURN BOOT ENABLE AND WRITE PROTECT BITS
SET_REG:PF7100:OTP_PAGE2:FADDR_STOP:0xFF
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0xFC
SET_REG:PF7100:OTP_PAGE2:FDATA:0xAA
SET_REG:PF7100:OTP_PAGE2:FCMD:0x87
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0xFD
SET_REG:PF7100:OTP_PAGE2:FDATA:0x55
SET_REG:PF7100:OTP_PAGE2:FCMD:0x87
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0xFE
SET_REG:PF7100:OTP_PAGE2:FDATA:0xAA
SET_REG:PF7100:OTP_PAGE2:FCMD:0x87
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0xFF
SET_REG:PF7100:OTP_PAGE2:FDATA:0x55
SET_REG:PF7100:OTP_PAGE2:FCMD:0x87

//Check FSTATUS register for the busy to go low
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS

//FORCE VDDOTP to 0V
SET_DPIN:PF7100:USBEN:low
SET_DPIN:PF7100:BSTEN:low
SET_DPIN:PF7100:VDDOTPEN:low

//OTP programming verification
GET_REG:PF7100:Functional:DEVICE_ID
SET_REG:PF7100:OTP_PAGE2:FADDR_START:0x00
SET_REG:PF7100:OTP_PAGE2:FADDR_STOP:0x48
SET_REG:PF7100:OTP_PAGE2:FCMD:0xAB
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA0
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA1
SET_REG:PF7100:OTP_PAGE2:FCMD:0xA4
//read sector status (must read 3Fh) and FSTATUS (must read 00h)
GET_REG:PF7100:OTP_PAGE2:SECT_STATUS
GET_REG:PF7100:OTP_PAGE2:FSTATUS
//read LOW CRC byte HIGH CRC byte (optional)
GET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF7100:OTP_MIRROR:OTP_S0_CRC_MSB

//If SECT_STATUS = 0x3F & FSTATUS = 0x00 part is programmed correctly.
//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES"

SET_DPIN:PF7100:TBBEN:low

//Rev,A
