//FS26 - OTP Editor
//file generated on  1 31 13:08:43 2024
//Device Type:FS26-D
//OTP ID:G6
//Customer:NXP
//Part Number:SFS2633AMDG6AD



//Test mode entry
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0000
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xD5A7
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xB8EE
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0F37


//Verify tet mode entry _expect 0x0100
GET_REG:FS26:M_TestMode:M_TM_STATUS1


//Set Main OTP Controller Parameters
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0100

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0000
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0002
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00DC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0008
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0038
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0009
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00DC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x000C
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00D2
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPPARAM0:0x01C8
SET_REG:FS26:M_TestMode:M_OTPPARAM1:0x0000
SET_REG:FS26:M_TestMode:M_OTPPARAM2:0x0002
SET_REG:FS26:M_TestMode:M_OTPPARAM3:0x2000
SET_REG:FS26:M_TestMode:M_OTPPARAM4:0x24BB

SET_REG:FS26:M_TestMode:M_OTPADDR:0x3E20


//MAIN_VOTP
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011B
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0010
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011C
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011D
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011E
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011F
//MAIN_OTP
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0030
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0120
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0040
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0121
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0122
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x00d4
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0123
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0124
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x008b
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0125
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x000a
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0126
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x00f3
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0127
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0015
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0128
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x00eb
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0129
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x004a
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012A
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012B
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x006b
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012C
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x002b
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012D
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x002b
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012E
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0001
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x012F
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0130
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0028
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0131
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0041
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0132
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0133
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0134
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0003
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0135
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0013
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0136
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x002a
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0137
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0047
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0138
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0047
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x0139
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x003f
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x013A
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0006
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x013B
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0006
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x013C
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x013D
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x013E

//Calcualte the CRC Registers for Main Sector
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0125
//Verify the CRC Registers
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0124

//Check Status Register to ensure CRC are correct.
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x003D
GET_REG:FS26:M_TestMode:M_MIRRORDATA
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x003E
GET_REG:FS26:M_TestMode:M_MIRRORDATA
GET_REG:FS26:M_TestMode:M_OTPSTATUS1

//-----------------------Burn Main OTP Registers  ----------------------
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0116
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

//-----------------------Burn Main Boot Enable and Write Protect ----------------------
SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF76
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0055
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF77
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AA
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF74
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0055
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF75
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AA
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
//----------------------------- END MAIN ----------------------------


//Fail Safe Test mode entry
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0000
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xD5A7
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xB8EE
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0F37

//Verify test mode entry
GET_REG:FS26:FS:FS_STATES

SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0100

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0000
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0002
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00DC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0008
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0038
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0009
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00DC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x000C
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00D2
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPPARAM0:0x01C8
SET_REG:FS26:FS_TestMode:FS_OTPPARAM1:0x0000
SET_REG:FS26:FS_TestMode:FS_OTPPARAM2:0x0002
SET_REG:FS26:FS_TestMode:FS_OTPPARAM3:0x2000
SET_REG:FS26:FS_TestMode:FS_OTPPARAM4:0x24BB

//Set the Start and End address.
SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x220F


//FAILSAFE_VOTP
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0080
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010A
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0044
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010B
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010C
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010D
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010E
//FAILSAFE_OTP
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0038
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010F
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0028
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0110
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x005f
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0111
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x00bb
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0112
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0033
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0113
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0114
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0115
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0116
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0117
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0118
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0077
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0119
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011A
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011B
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011C
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x007f
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011D
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011E
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x011F
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0120
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0121
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0122

//Calculate FS CRC bits
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0125
//Verify CRC Bits
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0124

//Verify the CRC Values
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0021
GET_REG:FS26:FS_TestMode:FS_MIRRORDATA
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x0022
GET_REG:FS26:FS_TestMode:FS_MIRRORDATA

//Check Controller status.
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS1

//----------------Start Burning Fuses ---------------------------------
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0116
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

//-------------Burn Boot Enable and Write Protect --------------------
SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF76
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF77
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AA
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF74
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF75
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AA
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

//---------------------------- END FAILSAFE ------------------------------

//Write main registers

//Test mode entry
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0000
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xD5A7
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xB8EE
SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0F37

//Verify tet mode entry _expect 0x0100
GET_REG:FS26:M_TestMode:M_TM_STATUS1

//Set Main OTP Controller Parameters
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0100

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0000
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0002
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00DC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0008
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0038
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x0009
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00DC
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPADDR:0x000C
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00D2
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0129

SET_REG:FS26:M_TestMode:M_OTPPARAM0:0x01C8
SET_REG:FS26:M_TestMode:M_OTPPARAM1:0x0000
SET_REG:FS26:M_TestMode:M_OTPPARAM2:0x0002
SET_REG:FS26:M_TestMode:M_OTPPARAM3:0x2000
SET_REG:FS26:M_TestMode:M_OTPPARAM4:0x24BB

SET_REG:FS26:M_TestMode:M_OTPADDR:0x1F1B

//MAIN_VOTP
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011B
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0010
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011C
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011D
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011E
SET_REG:FS26:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x011F

//Calcualte the CRC Registers for Main Sector
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0125
//Verify the CRC Registers
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0124

//Check Status Register to ensure CRC are correct.
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x001E
GET_REG:FS26:M_TestMode:M_MIRRORDATA
SET_REG:FS26:M_TestMode:M_MIRRORCMD:0x001F
GET_REG:FS26:M_TestMode:M_MIRRORDATA
GET_REG:FS26:M_TestMode:M_OTPSTATUS1

//-----------------------Burn Main VOTP Registers  ----------------------
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0116
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

//-----------------------Burn Main Boot Enable and Write Protect ----------------------
SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF7A
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0055
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF7B
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AA
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF78
SET_REG:FS26:M_TestMode:M_OTPDATA:0x0055
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0

SET_REG:FS26:M_TestMode:M_OTPADDR:0xFF79
SET_REG:FS26:M_TestMode:M_OTPDATA:0x00AA
SET_REG:FS26:M_TestMode:M_OTPCMD:0x0107
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
GET_REG:FS26:M_TestMode:M_OTPSTATUS0
//----------------------------- END MAIN ----------------------------



//Write Fail safe registers

//Fail Safe Test mode entry
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0000
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xD5A7
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xB8EE
SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0F37

//Verify test mode entry
GET_REG:FS26:FS:FS_STATES

SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0100

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0000
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0002
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00DC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0008
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0038
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0009
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00DC
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x000C
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00D2
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0129

SET_REG:FS26:FS_TestMode:FS_OTPPARAM0:0x01C8
SET_REG:FS26:FS_TestMode:FS_OTPPARAM1:0x0000
SET_REG:FS26:FS_TestMode:FS_OTPPARAM2:0x0002
SET_REG:FS26:FS_TestMode:FS_OTPPARAM3:0x2000
SET_REG:FS26:FS_TestMode:FS_OTPPARAM4:0x24BB

//Set the Start and End address.
SET_REG:FS26:FS_TestMode:FS_OTPADDR:0x0E0A


//FAILSAFE_VOTP
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0080
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010A
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0044
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010B
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010C
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010D
SET_REG:FS26:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x010E

//Calculate FS CRC bits
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0125
//Verify CRC Bits
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0124

//Verify the CRC Values an
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x000D
GET_REG:FS26:FS_TestMode:FS_MIRRORDATA
SET_REG:FS26:FS_TestMode:FS_MIRRORCMD:0x000E
GET_REG:FS26:FS_TestMode:FS_MIRRORDATA

//Check Controller status.
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS1

//----------------Start Burning Fuses ---------------------------------
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0116
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

//-------------Burn Boot Enable and Write Protect --------------------
SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF7A
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF7B
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AA
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF78
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x0055
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

SET_REG:FS26:FS_TestMode:FS_OTPADDR:0xFF79
SET_REG:FS26:FS_TestMode:FS_OTPDATA:0x00AA
SET_REG:FS26:FS_TestMode:FS_OTPCMD:0x0107
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0
GET_REG:FS26:FS_TestMode:FS_OTPSTATUS0

//---------------------------- END FAILSAFE ------------------------------


//Rev,A

