//PF5024 - OTP Editor
//file generated on lun. mars 7 13:15:54 2022
//Device Type:PF5024-B
//OTP ID:AV
//Customer:NXP
//Part Number:MPF5024CMBAVES

SET_DPIN:PF5024:PWRON:low
SET_DPIN:PF5024:WDI:low
SET_DPIN:PF5024:TBBEN:high

//MAIN_OTP
SET_REG:PF5024:OTP_MIRROR:OTP_I2C:0x19
SET_REG:PF5024:OTP_MIRROR:OTP_CTRL1:0x0a
SET_REG:PF5024:OTP_MIRROR:OTP_CTRL2:0x14
SET_REG:PF5024:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_FREQ_CTRL:0x8c
SET_REG:PF5024:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_WD_CONFIG:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_WD_EXPIRE:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_WD_COUNTER:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_FAULT_COUNTERS:0x21
SET_REG:PF5024:OTP_MIRROR:OTP_FAULT_TIMERS:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PWRDN_DLY2:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PWRUP_CTRL:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_SW1_VOLT:0xb1
SET_REG:PF5024:OTP_MIRROR:OTP_SW1_PWRUP:0x01
SET_REG:PF5024:OTP_MIRROR:OTP_SW1_CONFIG1:0x03
SET_REG:PF5024:OTP_MIRROR:OTP_SW1_CONFIG2:0x38
SET_REG:PF5024:OTP_MIRROR:OTP_SW2_VOLT:0xb1
SET_REG:PF5024:OTP_MIRROR:OTP_SW2_PWRUP:0x01
SET_REG:PF5024:OTP_MIRROR:OTP_SW2_CONFIG1:0x03
SET_REG:PF5024:OTP_MIRROR:OTP_SW2_CONFIG2:0x08
SET_REG:PF5024:OTP_MIRROR:OTP_SW3_VOLT:0xb1
SET_REG:PF5024:OTP_MIRROR:OTP_SW3_PWRUP:0x01
SET_REG:PF5024:OTP_MIRROR:OTP_SW3_CONFIG1:0x03
SET_REG:PF5024:OTP_MIRROR:OTP_SW3_CONFIG2:0x10
SET_REG:PF5024:OTP_MIRROR:OTP_SW4_VOLT:0xb1
SET_REG:PF5024:OTP_MIRROR:OTP_SW4_PWRUP:0x01
SET_REG:PF5024:OTP_MIRROR:OTP_SW4_CONFIG1:0x03
SET_REG:PF5024:OTP_MIRROR:OTP_SW4_CONFIG2:0x18
SET_REG:PF5024:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF5024:OTP_MIRROR:OTP_PROG_IDL:0x1d
SET_REG:PF5024:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF5024:OTP_MIRROR:OTP_SW_COMP1:0x24
SET_REG:PF5024:OTP_MIRROR:OTP_SW_COMP2:0x24
SET_REG:PF5024:OTP_MIRROR:OTP_SW_RAMP:0x00
SET_REG:PF5024:OTP_Misc:FCMD:0xA5
SET_REG:PF5024:OTP_Misc:FCMD:0xA4
SET_DPIN:PF5024:TBBEN:low
SET_DPIN:PF5024:PWRON:high

//Rev,B
