//PF5020 - OTP Editor
//file generated on  6 24 14:27:04 2021
//Device Type:PF5020-QM
//OTP ID:AC
//Customer:NXP
//Part Number:MPF5020CMMACES

SET_DPIN:PF5020:PWRON:low
SET_DPIN:PF5020:WDI:low
SET_DPIN:PF5020:TBBEN:high

//MAIN_OTP
SET_REG:PF5020:OTP_MIRROR:OTP_I2C:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL1:0x0a
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL2:0x0d
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF5020:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_WD_CONFIG:0x20
SET_REG:PF5020:OTP_MIRROR:OTP_WD_EXPIRE:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_WD_COUNTER:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FAULT_COUNTERS:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FAULT_TIMERS:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRDN_DLY2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRUP_CTRL:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x0f
SET_REG:PF5020:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_VOLT:0x74
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_PWRUP:0x0e
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_CONFIG2:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_VOLT:0xb1
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_PWRUP:0x04
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_CONFIG2:0x0b
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_VOLT:0x15
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_PWRUP:0x02
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_CONFIG2:0x13
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_VOLT:0x56
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_PWRUP:0x07
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_CONFIG:0x06
SET_REG:PF5020:OTP_MIRROR:OTP_VSNVS_CONFIG:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_ILIM_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PROG_IDL:0x0c
SET_REG:PF5020:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF5020:OTP_MIRROR:OTP_SW_COMP1:0x24
SET_REG:PF5020:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_SW_RAMP:0x0a
SET_REG:PF5020:OTP_Misc:FCMD:0xA5
SET_REG:PF5020:OTP_Misc:FCMD:0xA4
SET_DPIN:PF5020:TBBEN:low
SET_DPIN:PF5020:PWRON:high

//Rev,A
