//PF5020 - OTP Editor
//file generated on  6 24 14:27:04 2021
//Device Type:PF5020-QM
//OTP ID:AC
//Customer:NXP
//Part Number:MPF5020CMMACES

SET_DPIN:PF5020:PWRON:low
SET_DPIN:PF5020:WDI:low
SET_DPIN:PF5020:TBBEN:high

//MAIN_OTP
SET_REG:PF5020:OTP_MIRROR:OTP_I2C:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL1:0x0a
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL2:0x0d
SET_REG:PF5020:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF5020:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_WD_CONFIG:0x20
SET_REG:PF5020:OTP_MIRROR:OTP_WD_EXPIRE:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_WD_COUNTER:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FAULT_COUNTERS:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_FAULT_TIMERS:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRDN_DLY2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PWRUP_CTRL:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x0f
SET_REG:PF5020:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_VOLT:0x74
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_PWRUP:0x0e
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SW1_CONFIG2:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_VOLT:0xb1
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_PWRUP:0x04
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SW2_CONFIG2:0x0b
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_VOLT:0x15
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_PWRUP:0x02
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_CONFIG1:0x53
SET_REG:PF5020:OTP_MIRROR:OTP_SWND1_CONFIG2:0x13
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_VOLT:0x56
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_PWRUP:0x07
SET_REG:PF5020:OTP_MIRROR:OTP_LDO1_CONFIG:0x06
SET_REG:PF5020:OTP_MIRROR:OTP_VSNVS_CONFIG:0x03
SET_REG:PF5020:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_ILIM_BYPASS2:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PROG_IDH:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_PROG_IDL:0x0c
SET_REG:PF5020:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF5020:OTP_MIRROR:OTP_SW_COMP1:0x24
SET_REG:PF5020:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_REG:PF5020:OTP_MIRROR:OTP_SW_RAMP:0x0a
//---------Configure Controller----------
SET_REG:PF5020:OTP_Misc:FCMD:0x80
//This is probably not necessary
//MREF_Read_1_MSB
SET_REG:PF5020:OTP_Misc:FADDR_START:0x00
SET_REG:PF5020:OTP_Misc:FDATA:0xAC
SET_REG:PF5020:OTP_Misc:FCMD:0xA9

//MREF_Read_2_MSB
SET_REG:PF5020:OTP_Misc:FADDR_START:0x02
SET_REG:PF5020:OTP_Misc:FDATA:0xDC
SET_REG:PF5020:OTP_Misc:FCMD:0xA9

//8'b0011_1000
SET_REG:PF5020:OTP_Misc:FADDR_START:0x08
SET_REG:PF5020:OTP_Misc:FDATA:0x38
SET_REG:PF5020:OTP_Misc:FCMD:0xA9

//MREF_Read_3_MSB
SET_REG:PF5020:OTP_Misc:FADDR_START:0x09
SET_REG:PF5020:OTP_Misc:FDATA:0xDC
SET_REG:PF5020:OTP_Misc:FCMD:0xA9

//set FUSE Address to write to 0Ch
//set DATA to write to fuse address 0C
//run single data write command on OTP controller
SET_REG:PF5020:OTP_Misc:FADDR_START:0x0C
SET_REG:PF5020:OTP_Misc:FDATA:0xD2
SET_REG:PF5020:OTP_Misc:FCMD:0xA9

SET_REG:PF5020:OTP_Misc:MAX_PGM_TRIES:0x08
SET_REG:PF5020:OTP_Misc:MRR_SVDR_IN:0x13

SET_REG:PF5020:OTP_Misc:MR_TEST_H:0x00
SET_REG:PF5020:OTP_Misc:MR_TEST_L:0x02

SET_REG:PF5020:OTP_Misc:MREF_TEST_H:0x00
SET_REG:PF5020:OTP_Misc:MREF_TEST_L:0x00

SET_REG:PF5020:OTP_Misc:PULSE_DUR_1:0xBB
SET_REG:PF5020:OTP_Misc:PULSE_DUR_2:0x08

SET_REG:PF5020:OTP_Misc:FADDR_START:0x00
SET_REG:PF5020:OTP_Misc:FADDR_STOP:0x36

//---------SET CRC Values----------
SET_REG:PF5020:OTP_Misc:FCMD:0xA5
//This command may take 100-200us to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
SET_REG:PF5020:OTP_Misc:FCMD:0xA4
//This command may take 100-200us to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF5020:OTP_MIRROR:OTP_S0_CRC_MSB
GET_REG:PF5020:OTP_Misc:SECT_STATUS

//Burn the OTP fuses
//39. Apply VDDOTP = 7.8 V
//40. Wait 100 s for voltage at pin VDDOTP to stabilize

//---------Program OTP Fuses----------
SET_REG:PF5020:OTP_Misc:FCMD:0x96
//This command may take 50-100ms to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS

//---------BURN WP and BE bits----------
SET_REG:PF5020:OTP_Misc:FADDR_STOP:0xFF
SET_REG:PF5020:OTP_Misc:FADDR_START:0xFC
SET_REG:PF5020:OTP_Misc:FDATA:0xAA
SET_REG:PF5020:OTP_Misc:FCMD:0x87

//This command may take 1ms to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
SET_REG:PF5020:OTP_Misc:FADDR_START:0xFD
SET_REG:PF5020:OTP_Misc:FDATA:0x55
SET_REG:PF5020:OTP_Misc:FCMD:0x87

//This command may take 1ms to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
SET_REG:PF5020:OTP_Misc:FADDR_START:0xFE
SET_REG:PF5020:OTP_Misc:FDATA:0xAA
SET_REG:PF5020:OTP_Misc:FCMD:0x87

//This command may take 1ms to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
SET_REG:PF5020:OTP_Misc:FADDR_START:0xFF
SET_REG:PF5020:OTP_Misc:FDATA:0x55
SET_REG:PF5020:OTP_Misc:FCMD:0x87

//This command may take 1ms to complete.  To calculate the time one could poll the FSTATUS register for the busy to go low
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:FSTATUS
GET_REG:PF5020:OTP_Misc:SECT_STATUS

//Verify Mirror Registers = Fuse Value
GET_REG:PF5020:Functional:DEVICE_ID
SET_REG:PF5020:OTP_Misc:FADDR_START:0x00
SET_REG:PF5020:OTP_Misc:FADDR_STOP:0x36
SET_REG:PF5020:OTP_Misc:FCMD:0xAB
SET_REG:PF5020:OTP_Misc:FCMD:0xA0
SET_REG:PF5020:OTP_Misc:FCMD:0xA1
SET_REG:PF5020:OTP_Misc:FCMD:0xA4
GET_REG:PF5020:OTP_MIRROR:OTP_S0_CRC_LSB
GET_REG:PF5020:OTP_MIRROR:OTP_S0_CRC_MSB
GET_REG:PF5020:OTP_Misc:SECT_STATUS
GET_REG:PF5020:OTP_Misc:FSTATUS

//If SECT_STATUS = 0x3F & FSTATUS = 0x00 part is programmed correctly.
//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES"
//Alert the user to remove that the VDDOTP pin is set to 0V


SET_DPIN:PF5020:TBBEN:low

//Rev,A
