NXP® SemiconductorsMSE9S12E256_0L43X
Mask Set ErrataRev. April 17, 2012



MC9S12E256, Mask 0L43X


Introduction
This errata sheet applies to the following devices:

MC9S12E256



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts01493 S12_cpu Tagged breakpoints missed if tag attach and interrupt are simultaneous NO
MUCts01967 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03471 atd_10b16c ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work YES
MUCts03519 fts256k2 FTS256K2: Blind Spot in Data Compress Command Algorithm YES
MUCts03661 vreg_3v3 vreg_3v3.02.06: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry NO
MUCts03688 atd_10b16c ADC: conversion does not start with 2 consecutive writes to ATDCTL5 YES
MUCts03793 S12_mmc S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resources NO
MUCts04076 pwm_8b6c PWM: Emergency shutdown input can be overruled YES
MUCts04163 tim_16b4c TIM_16B4C: Output compare pulse is inaccurate YES
MUCts04223 pwm_8b6c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04225 pwm_8b6c PWM: Wrong output value after restart from stop or wait mode NO
MUCts04246 sci SCI: RXEDGIF occurs more times than expected in IR mode YES



Tagged breakpoints missed if tag attach and interrupt are simultaneous MUCts01493

Description

The errata concerns the DBG-CPU interface in DBG mode whilst configured

for tagging. If an interrupt occurs at the moment that a tag is attached
to an opcode being loaded into the instruction queue, the flag will get
set, but the part may not enter active BDM mode.

Using the DBG configuration BDM=DBGBRK=1, BEGIN=0, an event causing a
flag to be set should cause a break to BDM. The flag gets set, but the
part does not enter active BDM mode. The CPU executes the interrupt
service routine, instead, and returns to the correct position in the
program flow, but the breakpoint to BDM is missed.

The problem does not occur if the DBG module is configured for operation
in BKP mode (BKABEN=1). This is because, even if the flag bit is set,
the BKABEN bit is not cleared. On returning from the interrupt service
routine, the tag is re-applied when the PC is fetched after the
interrupt service routine, and the part enters BDM after the interrupt
service routine. In BKP mode with TRGSEL=0, no flags are set when a
taghit occurs.

In BKP mode with TRGSEL=1, the flag is also set erroneously on entering
the interrupt service routine. However, it is unlikely that a user would
be affected by the flag being set early (unless the service routine were
exceptionally long), due to the length of time needed to read out the
DBGSR (flag bits) over the BKGD pin; typically, during this time, the
part would enter active BDM when the tag is re-applied.

Workaround


None.



Possible manipulation of return address when exiting BDM active modeMUCts01967

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403

Description

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following
transmission.



Workaround


When disabling the slave SPI, CPHA should not be cleared at the same time. 




ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not workMUCts03471

Description

Starting a conversion with a write to ATDxCTL5 or on an external trigger

event, and aborting immediately afterwards with a write to ATDxCTL0,
ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the conversion process.

Workaround


Only write to ATDxCTL4 to abort an ongoing conversion sequence.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information
Subsection: Setting up and starting an A/D conversion
Subsection: Aborting an A/D conversion



FTS256K2: Blind Spot in Data Compress Command AlgorithmMUCts03519

Description

If the range of Flash addresses to be compressed is 32K or greater, the

data at one of the addresses will be effectively ignored. The address
affected is 32K from the upper address read in the data compress
algorithm, e.g., for an address range of 32K, the first data read in the
algorithm will not affect the final signature provided by the algorithm.


Workaround


Limit range of addresses to be compressed to less than 32K addresses.

Execute multiple data compress commands to compress larger Flash address
ranges.



vreg_3v3.02.06: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entryMUCts03661

Description

It is possible that after the device enters Stop or Pseudo-Stop mode it

may reset rather than wake up normally upon reception of the wake-up
signal.

CONDITIONS: This event will only happen provided ALL of the following
conditions are met:
1) Device is powered by the on-chip voltage regulator.
2) Device enters stop or pseudo-stop mode by execution of STOP
instruction by the CPU (provided the S-bit in CCR is cleared)
NOTE: The part enters stop mode either after 12 oscillator clock cycles
with the PLL disengaged or 3 PLL clock cycles and 8 oscillator clock
cycles with the PLL engaged after the STOP command is executed.
3) The wake-up signal is activated within a specific very short
window (typically 11ns long, not longer than 20ns). The position of the
window varies between different devices, however it never starts sooner
than 1.6µs and never ends later than 4.7µs after the stop mode entry.

This really narrow width of the susceptible window (20ns maximum) makes
the erratum unlikely to ever show in the applications life.

The incorrect behavior will never occur if ANY of the wake-up conditions
are met at the time when the stop mode entry is attempted (an enabled
interrupt is pending).

EFFECT:
If this incorrect behavior occurs, the device will Reset and indicate a
Low Voltage Reset (LVR) as the reset source.
The device will operate normally after the reset.

Workaround


None. 


--

Asynchronous Low Voltage Resets are possible in any microcontroller
application (due to power supply drops) and the integrated LVR and LVI
features and dedicated LVR reset vector are provided to manage this fact
cleanly. For best practice, the application's software should be written
to recover from a Low Voltage Reset in a controlled manner. An
application software written to deal with valid Low Voltage Resets
should correctly manage erroneous LVR events.

It can also be possible to avoid erroneous Low Voltage Resets from
synchronous wake-up events by configuring the application software to
ensure that the entry into stop occurs at such a time, in relation to
the wake-up event timer, that a wake-up event does not occur within
1.6µs to 4.7µs after Stop/Pseudo-Stop entry.



ADC: conversion does not start with 2 consecutive writes to ATDCTL5MUCts03688

Description

When the ATD is started with write to ATDCTL5

and, which is very unusual and not necessary,
within a certain period again started with write
to ATDCTL5. The conversion will not start at all.
This does only happen if the two consecutive writes to ATDCTL5 occur
within one "ATD clock period". An ATD clock period is defined by a full
rollover of the ATD clock prescaler. That is for example PRS[4:0] = 2 -
> (2+1)*2 = within 6 bus cycles.


Workaround


Only write once to ATDCTL5 when starting a conversion.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information Subsection: Setting up
and starting an A/D conversion Subsection: Aborting an A/D conversion



S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resourcesMUCts03793

Description

When writing or reading the internal BDM resources (address range $FF00

to $FFFF) via BDM hardware commands, the /XCS Chip Select signal is
erroneously driven low during the BDM access.

The /XCS signal is also driven low for CPU accesses performed to execute
BDM firmware when the CPU is in BDM active mode (BDMACT=1). This
includes the specific read/write cycle of the BDM firmware commands
READ_NEXT and WRITE_NEXT to access the targeted address of BDM firmware.

The R/W signal remains in read state in all these cases. The data
received by the above false external read accesses are discarded by the MCU.


Workaround


None. 




PWM: Emergency shutdown input can be overruledMUCts04076

Description

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.



Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 5 by setting the PWME5 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.





TIM_16B4C: Output compare pulse is inaccurateMUCts04163

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 1.1 (06 

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.









PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04223

Description

When the PWM is used in 16-bit (concatenation) channel and the 

emergency
shutdown feature is being used, after de-asserting PWM channel 5
(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show
the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.



Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04225

Description

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP4) cannot keep the state which is set by PWMLVL bit.




Workaround


None. 




SCI: RXEDGIF occurs more times than expected in IR modeMUCts04246

Description

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two
cases:

Case 1: due to re-sync of the RXD input, the received edge may be
delayed by one bus cycle. If an edge (bit = '0') is detected near
an SCI clock edge, the next edge (bit = '0') may be detected one
SCI clock later than expected due to re-sync logic.

Case 2: if external baud is slower than SCI receiver, the next edge
may be detected later than expected.

This glitch can be detected by the RXEDGIF circuit, but it does not
impact the final data result because the SCI receive and data recovery
logic takes samples at RT8, RT9, and RT10.




Workaround


Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit
faster than receiver baud by:
P > (1/16)/(SBR)
or
(P)(SBR)(16)> 1

Where SBR is baud of receiver, P is external baud faster ratio.
For example:
1.- When SBR = 16, P = 0.4%, this means the external baud should be at
least 0.4% faster than receiver.
2.- When SBR = 4, P = 1.6%, this means the external baud should be at
least 1.6% faster than receiver.

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is
solved, case 2 is also solved.


© NXP Semiconductors, Inc., 2012. All rights reserved.