NXP® SemiconductorsMSE9S12E128_0L15P
Mask Set ErrataRev. April 17, 2012



MC9S12E128, Mask 0L15P


Introduction
This errata sheet applies to the following devices:

MC9S12E128



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts00755 S12_bdm BDM: ACK conflict exiting STOP YES
MUCts00762 S12_cpu DBG: CPU erroneously causes BSRs to be recorded in trace buffer YES
MUCts00763 S12_dbg DBG full mode triggers do not work properly in register space writes NO
MUCts00765 S12_dbg Forced trigger delay before taking effect YES
MUCts00775 fts128k1 Protection transitions NO
MUCts00779 S12_dbg DBG: LOOP1 mode with break to BDM captures all change of flow instructions YES
MUCts00785 atd_10b16c Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags YES
MUCts00808 fts128k1 Additional write protection exists via mirroring. NO
MUCts00821 crg PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset YES
MUCts00857 fts128k1 Flash: ACCERR is not set for a Byte Access YES
MUCts00903 fts128k1 STOP instruction may set flash ACCERR flag. YES
MUCts01006 fts128k1 Array writes immediately after FPROT write do not set PVIOL flag. YES
MUCts01023 atd_10b16c CCF flags in ATDSTAT2/1 registers might fail to set NO
MUCts01033 atd_10b16c Clearing of CCF flags in ATDSTAT2/1 by write of ATDCTL5 might not work YES
MUCts01079 S12_dbg DBG: BDM firmware code execution may erroneously cause forced trigger YES
MUCts01254 pmf_15b6c PMF: Inability to clear reload interrupts when in single time base mode. YES
MUCts01430 S12_cpu Tagged breakpoints missed if tag attach and interrupt are simultaneous NO
MUCts01966 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02142 mcu_9e128 Reduced flash program temperature range and increased programming time NO
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03475 atd_10b16c ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work YES
MUCts03658 vreg_3v3 vreg_3v3.02.03: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry NO
MUCts03793 S12_mmc S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resources NO
MUCts04076 pwm_8b6c PWM: Emergency shutdown input can be overruled YES
MUCts04162 tim_16b4c TIM_16B4C: Output compare pulse is inaccurate YES
MUCts04223 pwm_8b6c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04225 pwm_8b6c PWM: Wrong output value after restart from stop or wait mode NO
MUCts04248 sci SCI: RXEDGIF occurs more times than expected in IR mode YES



BDM: ACK conflict exiting STOPMUCts00755

Description

When using the Background Debugger to debug 

code which contains STOP instructions, the
host debugger can lose clock sync with the
target device. If the ACK protocol is enabled,
a target command which is expecting to send
and ACK pulse, can conflict with a host issued
SYNC command attempting to re-establish clock
sync between the host and target.

Workaround


The ACK protocol can be disabled when debugging

source code which contains STOP instructions.
The host SYNC command may then be used to re-establish
clock sync between the host and target after
a STOP instruction.



DBG: CPU erroneously causes BSRs to be recorded in trace bufferMUCts00762

Description

The BSR instruction is recognized as a change of flow instruction and

thus causes the trace buffer to be loaded with its destination address.
Since the BSR instruction always branches to the relative address
specified in the instruction, the information stored in the trace buffer
at a BSR is not useful. Thus code making regular use of the BSR
instruction will result in considerable redundancy in trace buffer
contents.


Workaround


The severity of this bug is directly related to the frequency of BSR 

instruction use. Thus to reduce the impact of this bug, use of the BSR
instruction should be avoided wherever possible.





DBG full mode triggers do not work properly in register space writesMUCts00763

Description

Write accesses to the registers can cause erroneous trigger action when 

using full mode (address AND data) triggers.

A AND B Trigger Mode
Writing to the registers using the A AND B trigger mode may not trigger
the start of FIFO capture even though a valid successful compare should
have occurred. Rarely, the same bug will cause an erroneous successful
trigger even though an address and data match has not occurred.

A AND NOT B Trigger Mode
Writing to the registers using the A AND NOT B trigger mode may cause
an erroneous successful trigger even though an address and data match
has not occurred. Rarely, the same bug will prevent a trigger from
being generated, even though a valid successful compare should have
occurred. Reads of registers and reads and writes to non-register space
are not affected by this erratum.

Workaround


No workaround exists






Forced trigger delay before taking effectMUCts00765

Description

Several cycles are required after enabling a forced trigger before it

takes effect.

This is expected behavior but not clearly noted in the user guide. Thus
it is classed as customer information (as opposed to errata).

Workaround


Take into account that extra cycles are required when using forced

breakpoints.



Protection transitionsMUCts00775

Description

It is possible to perform illegal flash block protection scheme

(scenario) transitions. The flash protection mechanism is designed to
prevent the flash protection scheme from being switched to a state of
lesser protection in the event of accidental writes to the flash
protection (FPROT) register. Certain transitions to states of greater
protection should be allowed as detailed in the flash block user guide.

A bug in the protection scheme has made it possible to transition to
protection states other than the states prescribed in the flash block
user guide by writing to the flash protection register. The transitions
include transitions to states of greater and lesser protection,
depending on the start state and the value written to the protection
register.

Workaround


There is no workaround, although this problem will not be seen if

illegal protection transitions are not attempted.



DBG: LOOP1 mode with break to BDM captures all change of flow instructionsMUCts00779

Description

When using LOOP1 debug mode with break to BDM, the trace buffer captures

all change of flow instructions, as if operating in normal capture mode.
This bug is restricted to LOOP1 mode with break to BDM activated, break
to SWI mode is unaffected by this erratum.


Workaround


When using LOOP1 mode use only break to SWI, not break to BDM. This 

will guarantee correct operation.



Write to ATDCTL5 may not clear SCF, CCF and ASCIF flagsMUCts00785

Description

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)
ASCIF flags remain set and are NOT cleared by a write to ATDCTL5.

Workaround


1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).
2. Write to ATDCTL5 twice.



Additional write protection exists via mirroring.MUCts00808

Description

Flash protection is mirrored once (hence appears twice) in every flash

block. The mirrored protection will occur four pages lower than the
intended protection. For example, if flash page $3F is protected, the
mirrored protection, specified by the FPROT register setting for the
respective block, will occur in flash page $3B. If flash page $3E is
protected, the mirrored protection will occur in page $3A.


Workaround


None.



PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or resetMUCts00821

Description

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.

If

1) pll_clock (PLLON=1) is running
and
2) 2 < osc_clock/pll_clock < 3
and
3) full stop mode is entered (STOP instruction with PSTP Bit =0)

there is a small possibility that when entering full stop mode the chip
reacts as follows:
1) if self clock mode is disabled (SCME=0) monitor reset is asserted.
The system does NOT enter stop mode.
or
2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)
a self clock mode interrupt is generated. The SCMIF flag is set.
The system does NOT enter stop mode.
or
3) if SCME=1 and SCMIE=0 the system will enter full stop mode.
But after wakeup self clock mode is entered without doing the
specified clock quality check. The SCMIF flag is set.

Workaround


1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or
2) if you really require osc_clock/pll_clock ratio between 2 and 3
do the following before going into stop.
a) deselect PLL (PLLSEL=0)
b) turn off PLL (PLLON=0)
c) enter stop
d) exiting stop: turn on PLL again (PLLON=1)



Flash: ACCERR is not set for a Byte AccessMUCts00857

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations. 




STOP instruction may set flash ACCERR flag.MUCts00903

Description

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the FSTAT flash status register.

Workaround


The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded.



Array writes immediately after FPROT write do not set PVIOL flag.MUCts01006

Description

A write to the flash protection register that is immediately followed by

a flash array write will not set the PVIOL protection violation flag.

Example:
MOVB #$FB FPROT //protect lower portion of flash page $3E
STD #$55AA #$8080 //write to protected address (PVIOL flag expected,
but does not occur)

Workaround


Perform a legal write of a register immediately after writing to the

FPROT register, before writing to the flash array.

Example:
MOVB #$FB FPROT //protect lower portion of flash page $3E
MOVB #$30 FSTAT //clear error flags (legal write to register)
STD #$55AA #$8080 //write to protected address (PVIOL flag sets to show
protection violation)



CCF flags in ATDSTAT2/1 registers might fail to setMUCts01023

Description

The setting of the CCF15-0 flags in ATDSTAT2/1 registers

is not independent of the clearing.
A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)
which occurs in exactly the same bus cycle as the setting of any other
flag CCFy (x,y = 0,1,..,15; x!=y) masks the setting of CCFy.
CCFy will not set in this special case although the corresponding
conversion has completed and the result (ATDDRy) is valid.

Workaround


None.



Clearing of CCF flags in ATDSTAT2/1 by write of ATDCTL5 might not workMUCts01033

Description

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT2/1 registers.
This does not always work if the write to ATDCTL5 register
occurs near the end of an ongoing conversion.
Although all CCF flags are cleared one CCF flag might be
set again within the 1st ATD clock period of the new conversion.


Workaround


If the unexpected setting of one CCF flag can not be

accepted by the application one of the following
workarounds can be taken:
1) o Abort conversion (e.g. by write to ATDCTL3)
o pause for 2 ATD clock periods
o Start new conversion
2) o ignore first conversion sequence and clear CCF flags



DBG: BDM firmware code execution may erroneously cause forced triggerMUCts01079

Description

Breakpoints are temporarily disabled while the MCU is executing BDM

firmware code when operating in active BDM mode. It logically follows
that debug module triggers are disabled in the same manner. While tagged
triggers are disabled, forced triggers are not and therefore may cause
the debug module to trigger erroneously.

In most circumstances this will only be a problem in outside range
trigger mode. In order to see an erroneous trigger in another trigger
mode, a forced trigger must be configured in the BDM firmware address
range ($FF00-$FF80) and an exact address bus match must occur. This
memory area would typically contain interrupts, vectors or program code,
and would therefore be a very unlikely location for the configuration of
a forced trigger address.

Workaround


Outside range trigger mode should not be used when configuring forced

triggers if the trigger range contains the memory area where the BDM
firmware code resides ($FF00-$FF80) and the user intends to operate the
MCU in active BDM mode.





PMF: Inability to clear reload interrupts when in single time base mode.MUCts01254

Description

When the PMF is set to single time base mode (MTG = 0) reload 

interrupts from generators B and C can not be cleared by simply
clearing the reload flag in the PMFFQCA register.

In signle time base mode (MTG=0) there is no way to clear reload
interrupts B and C. These interrupts will always be pending when using
reload interrupts in signle time base mode only.


Workaround


Please reference Engineering Bulletin EB636 for a complete explanation

of the workaround.



Tagged breakpoints missed if tag attach and interrupt are simultaneous MUCts01430

Description

The problem concerns the DBG-CPU interface in DBG mode whilst tagging if

an interrupt occurs at the moment that a tag is attached to an opcode
being loaded into the instruction queue.

If the DBG module is configured with BDM=DBGBRK=1, BEGIN=0 an event
causing a flag to be set should cause a break to BDM. The symptom is
that the flag gets set but the part does not enter active BDM mode. The
CPU executes the interrupt service routine instead and returns to the
correct position in the program flow but the breakpoint to BDM is
missed.

The problem does not occur if the DBG module is configured for operation
in BKP mode (BKABEN=1). This is because even if the flag bit is set,
BKABEN bit is not cleared. Thus on returning from the interrupt service
routine the tag is re-applied when the PC is fetched after the interrupt
service routine. Thus the part enters BDM after the interrupt service
routine.

In BKP mode with TRGSEL=0 no flags are set when a taghit occurs.
In BKP mode with TRGSEL=1 the flag is also set erroneously, on entering
the interrupt service routine. However the user would typically not
notice the flag being set early unless the service routine were
exceptionally long, because of the large time needed to read out the
DBGSR (flag bits) over the BKGD pin. In the meantime the part would
typically have entered active BDM anyway when the tag is re-applied.

Furthermore this does not occur on the older BKP module which does not
feature flags to indicate tag hits.

Workaround


None.



Possible manipulation of return address when exiting BDM active modeMUCts01966

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



Reduced flash program temperature range and increased programming timeMUCts02142

Description

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take
place between temperatures of 0C and 125C ambient.

In addition, the flash program times have been increased as follows:

Programming Time
Min. Max.
Single Word Program (Tswpgm) 66.0us 99.2us
Flash Row Program - Consecutive Word (Tbwpgm) 40.4us 57.8us
Flash Row Program - 64 words (Tbrpgm) 2608.7us 3742.7us

Actual programming time will vary between the above bounds depending on
flash clock and bus clock frequencies.

Important Notes:
1) Program time is internally controlled by the flash state machine.
No action needs to be taken by users in connection with this erratum.
2) Both flash erase and flash read temperature specifications and
operation times are unaffected by this erratum.
3) EEPROM is unaffected by this erratum.
~



Workaround


None.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403

Description

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following
transmission.



Workaround


When disabling the slave SPI, CPHA should not be cleared at the same time. 




ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not workMUCts03475

Description

Starting a conversion with a write to ATDxCTL5 or on an external trigger

event, and aborting immediately afterwards with a write to ATDxCTL0,
ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the conversion process.

Workaround


Only write to ATDxCTL4 to abort an ongoing conversion sequence.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information
Subsection: Setting up and starting an A/D conversion
Subsection: Aborting an A/D conversion



vreg_3v3.02.03: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entryMUCts03658

Description

It is possible that after the device enters Stop or Pseudo-Stop mode it

may reset rather than wake up normally upon reception of the wake-up
signal.

CONDITIONS: This event will only happen provided ALL of the following
conditions are met:
1) Device is powered by the on-chip voltage regulator.
2) Device enters stop or pseudo-stop mode by execution of STOP
instruction by the CPU (provided the S-bit in CCR is cleared)
NOTE: The part enters stop mode either after 12 oscillator clock cycles
with the PLL disengaged or 3 PLL clock cycles and 8 oscillator clock
cycles with the PLL engaged after the STOP command is executed.
3) The wake-up signal is activated within a specific very short
window (typically 11ns long, not longer than 20ns). The position of the
window varies between different devices, however it never starts sooner
than 1.6µs and never ends later than 4.7µs after the stop mode entry.

This really narrow width of the susceptible window (20ns maximum) makes
the erratum unlikely to ever show in the applications life.

The incorrect behavior will never occur if ANY of the wake-up conditions
are met at the time when the stop mode entry is attempted (an enabled
interrupt is pending).

EFFECT:
If this incorrect behavior occurs, the device will Reset and indicate a
Low Voltage Reset (LVR) as the reset source.
The device will operate normally after the reset.

Workaround


None. 


--

Asynchronous Low Voltage Resets are possible in any microcontroller
application (due to power supply drops) and the integrated LVR and LVI
features and dedicated LVR reset vector are provided to manage this fact
cleanly. For best practice, the application's software should be written
to recover from a Low Voltage Reset in a controlled manner. An
application software written to deal with valid Low Voltage Resets
should correctly manage erroneous LVR events.

It can also be possible to avoid erroneous Low Voltage Resets from
synchronous wake-up events by configuring the application software to
ensure that the entry into stop occurs at such a time, in relation to
the wake-up event timer, that a wake-up event does not occur within
1.6µs to 4.7µs after Stop/Pseudo-Stop entry.



S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resourcesMUCts03793

Description

When writing or reading the internal BDM resources (address range $FF00

to $FFFF) via BDM hardware commands, the /XCS Chip Select signal is
erroneously driven low during the BDM access.

The /XCS signal is also driven low for CPU accesses performed to execute
BDM firmware when the CPU is in BDM active mode (BDMACT=1). This
includes the specific read/write cycle of the BDM firmware commands
READ_NEXT and WRITE_NEXT to access the targeted address of BDM firmware.

The R/W signal remains in read state in all these cases. The data
received by the above false external read accesses are discarded by the MCU.


Workaround


None. 




PWM: Emergency shutdown input can be overruledMUCts04076

Description

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.



Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 5 by setting the PWME5 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.





TIM_16B4C: Output compare pulse is inaccurateMUCts04162

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.02 (06 

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.










PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04223

Description

When the PWM is used in 16-bit (concatenation) channel and the 

emergency
shutdown feature is being used, after de-asserting PWM channel 5
(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show
the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.



Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04225

Description

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP4) cannot keep the state which is set by PWMLVL bit.




Workaround


None. 




SCI: RXEDGIF occurs more times than expected in IR modeMUCts04248

Description

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two
cases:

Case 1: due to re-sync of the RXD input, the received edge may be
delayed by one bus cycle. If an edge (bit = '0') is detected near
an SCI clock edge, the next edge (bit = '0') may be detected one
SCI clock later than expected due to re-sync logic.

Case 2: if external baud is slower than SCI receiver, the next edge
may be detected later than expected.

This glitch can be detected by the RXEDGIF circuit, but it does not
impact the final data result because the SCI receive and data recovery
logic takes samples at RT8, RT9, and RT10.




Workaround


Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit
faster than receiver baud by:
P > (1/16)/(SBR)
or
(P)(SBR)(16)> 1

Where SBR is baud of receiver, P is external baud faster ratio.
For example:
1.- When SBR = 16, P = 0.4%, this means the external baud should be at
least 0.4% faster than receiver.
2.- When SBR = 4, P = 1.6%, this means the external baud should be at
least 1.6% faster than receiver.

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is
solved, case 2 is also solved.


© NXP Semiconductors, Inc., 2012. All rights reserved.