NXP® SemiconductorsMSE9S12DP512_0L00M
Mask Set ErrataRev. February 13, 2011



MC9S12DP512, Mask 0L00M


Introduction
This errata sheet applies to the following devices:

MC9S12DP512, MC9S12DT512, MC9S12DJ512, MC9S12A512



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts00735 atd_10b8c Flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set YES
MUCts00755 S12_bdm BDM: ACK conflict exiting STOP YES
MUCts00784 atd_10b8c Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags YES
MUCts00807 fts512k4 Additional write protection exists via mirroring. NO
MUCts00821 crg PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset YES
MUCts00865 fts512k4 Flash: ACCERR is not set for a Byte Access YES
MUCts00866 eets4k EE: ACCERR is not generated for a Byte Access YES
MUCts00904 fts512k4 STOP instruction may set flash ACCERR flag. YES
MUCts00991 eets4k STOP instruction may set EEPROM ACCERR flag. YES
MUCts01011 ect_16b8c ECT: Input pulse shorter than delay counter period recognised as a valid YES
MUCts01029 atd_10b8c CCF flags in ATDSTAT1 register might fail to set NO
MUCts01039 atd_10b8c ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work YES
MUCts01094 mscan MSCAN: Data byte corrupted in receive buffer YES
MUCts01104 mscan MSCAN: Time stamp corrupted in receive buffer YES
MUCts01112 SFC0002_16A4_HDR EEPROM Reliability Errata NO
MUCts01346 mscan MSCAN: Message erroneously accepted if bus error in bit 6 of EOF YES
MUCts01966 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02382 eets4k EEPROM Program Failure during Sector-Modify YES
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03473 atd_10b8c ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work YES
MUCts03572 mscan MSCAN: Corrupt ID may be sent in early-SOF condition YES
MUCts04073 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04108 ect_16b8c ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 YES
MUCts04151 ect_16b8c ECT_16B8C: Output compare pulse is inaccurate YES
MUCts04199 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode YES
MUCts04203 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode YES



Flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously setMUCts00735

Description

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.
Writing '1' to the respective flag has no effect.

The ETORF flag is also set by a non-active edge, e.g. falling edge
trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and
rising edges while conversion is in progress.

Workaround


SCF 

1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL5 (a new conversion sequence is started)
b. If AFFC=1 a result register is read
ETORF
1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence
is aborted)
b. Write to ATDCTL5 (a new conversion sequence is started)
2. Avoid external trigger edges during conversion process by using short
pulses
3. Ignore ETROF flag

FIFOR
1. Use the alternative flag clearing mechanism:
a. Start a new conversion sequence
(write to ATDCTL5 or external trigger)



BDM: ACK conflict exiting STOPMUCts00755

Description

When using the Background Debugger to debug 

code which contains STOP instructions, the
host debugger can lose clock sync with the
target device. If the ACK protocol is enabled,
a target command which is expecting to send
and ACK pulse, can conflict with a host issued
SYNC command attempting to re-establish clock
sync between the host and target.

Workaround


The ACK protocol can be disabled when debugging

source code which contains STOP instructions.
The host SYNC command may then be used to re-establish
clock sync between the host and target after
a STOP instruction.



Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags MUCts00784

Description

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)
ASCIF flags remain set and are NOT cleared by a write to ATDCTL5

Workaround


1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).
2. Write to ATDCTL5 twice.



Additional write protection exists via mirroring.MUCts00807

Description

Flash protection is mirrored once (hence appears twice) in every flash

block. The mirrored protection will occur four pages lower than the
intended protection. For example, if flash page $3F is protected, the
mirrored protection, specified by the FPROT register setting for the
respective block, will occur in flash page $3B. If flash page $3E is
protected, the mirrored protection will occur in page $3A.

Workaround


None. 




PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or resetMUCts00821

Description

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.

If

1) pll_clock (PLLON=1) is running
and
2) 2 < osc_clock/pll_clock < 3
and
3) full stop mode is entered (STOP instruction with PSTP Bit =0)

there is a small possibility that when entering full stop mode the chip
reacts as follows:
1) if self clock mode is disabled (SCME=0) monitor reset is asserted.
The system does NOT enter stop mode.
or
2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)
a self clock mode interrupt is generated. The SCMIF flag is set.
The system does NOT enter stop mode.
or
3) if SCME=1 and SCMIE=0 the system will enter full stop mode.
But after wakeup self clock mode is entered without doing the
specified clock quality check. The SCMIF flag is set.

Workaround


1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or
2) if you really require osc_clock/pll_clock ratio between 2 and 3
do the following before going into stop.
a) deselect PLL (PLLSEL=0)
b) turn off PLL (PLLON=0)
c) enter stop
d) exiting stop: turn on PLL again (PLLON=1)



Flash: ACCERR is not set for a Byte AccessMUCts00865

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations. 




EE: ACCERR is not generated for a Byte AccessMUCts00866

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations.  




STOP instruction may set flash ACCERR flag.MUCts00904

Description

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the FSTAT flash status register.

Workaround


The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded.



STOP instruction may set EEPROM ACCERR flag.MUCts00991

Description

If the ECLKDIV EEPROM clock divider register has been loaded, and the

EEPROM is not executing a command (EEPROM CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the ESTAT EEPROM status register.

Workaround


The ACCERR bit in the ESTAT register must be cleared after the execution

of a STOP instruction if the ECLKDIV register has been loaded.



ECT: Input pulse shorter than delay counter period recognised as a validMUCts01011

Description

According to the observation, input pulse (high/low) whose pulse width

is shorter than delay counter window is mistakenly recognized as as
valid pulse. Hence the ic flags will be set and may result in an IRQ if
IRQ is enabled.



Workaround


A software workaround is available.


User software should check the logic level of the input capture pin
within the interrupt service routine and compare this with the logic
level when the input is not asserted. This can be performed using the
appropriate registers in the port integration module.

If the pin reads the logic level of the inactive state, the pulse is
shorter than the time defined in the delay counter control register
plus the interrupt latency. In this case, the pulse triggering the
input capture is not valid (too short), hence the interrupt can be
acknowledged and exited without further action taking place. If the pin
reads the logic level of the active state, the input pulse is valid and
the interrupt should be acknowledged and the correct input capture
service routine executed.

The effectiveness of this workaround must be evaluated by identifying
the worst case latency involved in the call of the ISR. To maximise the
effectiveness of pulse rejection, users must consider checking the
value in the capture register against the free-running timer on every
new capture.



CCF flags in ATDSTAT1 register might fail to setMUCts01029

Description

The setting of the CCF7-0 flags in ATDSTAT1 register

is not independent of the clearing.
A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)
which occurs in exactly the same bus cycle as the setting of any other
flag CCFy (x,y = 0,1,..,7; x!=y) masks the setting of CCFy.
CCFy will not set in this special case although the corresponding
conversion has completed and the result (ATDDRy) is valid.

Workaround


None.



ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not workMUCts01039

Description

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.
This does not always work if the write to ATDCTL5 register
occurs near the end of an ongoing conversion.
Although all CCF flags are cleared one CCF flag might be
set again within the 1st ATD clock period of the new conversion.

Workaround


If the unexpected setting of one CCF flag can not be

accepted by the application one of the following
workarounds can be taken:
1) Abort conversion (e.g. by write to ATDCTL3)
Pause for 2 ATD clock periods
Start new conversion
2) Ignore first conversion sequence and clear CCF flags




MSCAN: Data byte corrupted in receive bufferMUCts01094

Description

When the foreground receive buffer (RxFG) is read with the Receiver Full

Flag (RXF) set, the value of one or more data bytes may be incorrect due
to corruption after the message reception. The corruption can occur at
the end of a message transmission from any of the three transmit message
buffers of the same msCAN module. The affected data byte is overwritten
by a byte of the corrupting transmit buffer's Time Stamp Register, TSRH
for even, TSRL for odd addresses affected, respectively. The value
written is zero ($00) if the internal timer has not been enabled (TIME=0
in CANCTL0).

The corruption can only occur if all of the following three conditions
are met:

1. Rx and Tx message length relationship
If the number of data bytes transmitted, n, is five or less, Data
Segment Register (n+2) in RxFG is corrupted, i.e. DSR2 if n=0, .., DSR7
if n=5.
No corruption occurs for n > 5. Also, DSR0 and DSR1 are never affected.

2. Timing
A received message may contain corrupted data if RxFG is read after the
end of a message transmission from the same msCAN module.
No corruption is seen if all received messages are read within the time
window beginning when RXF is set and ending with the completion of
transmission of a subsequent message by the same msCAN module (the
'green window'). The width of the green window depends on many factors:
application software (Tx message scheduling, Rx/Tx interrupt priorities,
etc.), bus load, baud rate, and transmit message length. The minimum
(guaranteed) green window width is 376us for 125kbps, for example. This
minimum value occurs only in case of a transmit message following
back-to-back to the receive message, and for zero data bytes and zero
stuff bits. The green window width inversely scales with the baud rate.

3. Receive FIFO Buffer #
Only receive buffer 0 (Rx0) of the 5-stage FIFO can be affected.
At least four out of every five messages received are not affected.

Workaround


In affected systems where the lengths of messages can be adjusted, using

six or more bytes for transmission eliminates the issue completely.
Systems using an MCU with unused msCAN modules should use one to
transmit only and one to receive only, to completely avoid the issue.
For other systems the likelihood of problem occurrence can be further
reduced by maximizing the receive interrupt priority, i.e. use CAN0 for
the most critical bus in a multi-bus application, and/or promoting the
msCAN receive interrupt to highest priority using the HPRIO register.
In (control) systems where the signal representation can be adjusted,
and the time stamp is not used (TIME=0), mapping $00 to an 'illegal'
signal would allow problem detection and appropriate software means of
reaction.
In systems where all byte values are legal (e.g. data download),
checksums and/or parities can be used to signal problem occurrence and
allow for proper handling (e.g. request for retransmission).
Alternatively, the use of data filter algorithms may suppress or at
least reduce the effect of the problem.



MSCAN: Time stamp corrupted in receive bufferMUCts01104

Description

When the foreground receive buffer (RxFG) is read, with the Receiver

Full Flag (RXF) set, the value of the Time Stamp Register may be
incorrect due to corruption. The Time Stamp Register is written
correctly when the message is received, but may be overwritten by the
timer value at the end of a subsequent reception. The corruption can
only occur close to a data overrun, when the receive buffer FIFO is
full.

The problem occurs whenever the following two conditions are met:

1. Receive buffer system is full
All five receive buffers contain valid messages waiting to be read by
the application.

2. Another valid message is seen on the bus. This message must be sent
from another node, i.e. it must not be transmitted from the respective
msCAN module itself.

At the end of the message in 2. the Time Stamp Register of the oldest
message in the receive FIFO is overwritten.

Note: if the message in 2. passes the message filter system the Overrun
Interrupt Flag (OVRIF) is also set.

Workaround


The application software has to ensure to read the receive messages in

due time to avoid data overrun in any case. This will automatically
minimize the risk of a Time Stamp Register overwrite event.



EEPROM Reliability ErrataMUCts01112

Description

EEPROM cycling performance is 10K cycles across the device operating

temperature range.





Workaround


None.



MSCAN: Message erroneously accepted if bus error in bit 6 of EOFMUCts01346

Description

If a particular error condition occurs within the end of frame segment

(EOF) of a CAN message, the msCAN module recognises and accepts a
non-valid message as being valid, contrary to the CAN specification. The
msCAN module incorrectly validates messages after five recessive bits of
the end of frame instead of after six bits. If a bus error occurs during
the sixth bit of end of frame, the msCAN module will already have
accepted the message as valid, even although an error frame is
transmitted and the receive error counter is incremented.

The CAN protocol states that message validation differs between bus
transmitter and receiver devices (refer to part B, section 5 of CAN
protocol for details). In the case where the 7th bit of the EOF segment
is dominant, the message is valid for the receiver but not for the
transmitter. This erratum extends this case to the 6th bit of the EOF
segment.

Workaround


This erratum will not be an issue if the application software is

protected against the known double receive problem of the CAN protocol.
This problem occurs when a message is not recognised as valid by the
transmitter, but is recognised as valid by a receiver, as described
above. When this happens, the message is re-transmitted and hence the
receiver will receive the same message twice.



Possible manipulation of return address when exiting BDM active modeMUCts01966

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



EEPROM Program Failure during Sector-ModifyMUCts02382

Description

At oscillator frequencies above 4MHz the Program step of the EEPROM

Sector-Modify command can fail depending on the bus frequency. As a
result, no programming of the EEPROM occurs. There is no impact to the
Erase step of the Sector-Modify command. Since a partial programming of
the word cannot occur, there is not a reliability issue caused by the
Sector-Modify command if the programmed word is verified.

Oscillator Bus
Frequency Frequency
---------- ----------------------
4MHz No Issue
8MHz Fbus <20MHz : No issue
16MHz Fbus <16MHz : No issue




Workaround


Use seperate Erase and Program commands in place of the Sector-Modify

command. If the Sector-Modify command is used and fails the program step
as confirmed by a user verification step, a Program command alone can be
used to effectively complete the operation since the erase step does
successfully erase the sector.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403

Description

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following
transmission.



Workaround


When disabling the slave SPI, CPHA should not be cleared at the same time. 




ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not workMUCts03473

Description

Starting a conversion with a write to ATDxCTL5 or on an external 

trigger event, and aborting immediately afterwards with a write to
ATDxCTL0, ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the
conversion process.




Workaround


Only write to ATDxCTL4 to abort an ongoing conversion sequence.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information
Subsection: Setting up and starting an A/D conversion
Subsection: Aborting an A/D conversion






MSCAN: Corrupt ID may be sent in early-SOF conditionMUCts03572

Description

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is
sampled leading to an early-SOF*.

The CRC is calculated from the resulting bit stream so that the
receiving nodes will still validate the message.

An early-SOF condition may only occur if the oscillators in the network
operate at a tolerance range which could lead to a cumulated phase error
after 11 bit times larger than phase segment 2.

In case arbitration is lost during transmission of the corrupt
identifier, a non-corrupted ID will be sent with the next attempt if the
transmit request remains active.

*The CAN protocol condition referred to as 'early-SOF' in this erratum
is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,
and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B.

Workaround


Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided
when calculating the maximum oscillator tolerance of the overall CAN
system. The phase error after 11 bit times due to the oscillator
tolerance should be smaller than phase segment 2.

If an early-SOF cannot be avoided the following methods will provide
prevention:

- Assigning the same value to all upper eight ID bits in the network
- Allocating dedicated data length codes (DLC) to every identifier used
in the network and checking for correspondence after reception
- Assigning only IDs (x) which do not consist of a combination of other
assigned IDs (y,z) and using the acceptance filters to reject
erroneous messages, i.e.
- for standard frames: IDx[11:0] != {IDy[11:3], IDz[2:0]}
- for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]}



PWM: Emergency shutdown input can be overruledMUCts04073

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1MUCts04108

Description

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a
read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.


Details:

When any of the buffered input capture channels 0 - 3 are configured
for buffered/queue mode (BUFEN=1, LATQ=0) each of the channel’s input
capture holding registers and each channel’s associated pulse
accumulator and its holding register are enabled. When the input
capture channel is enabled by writing to a channel’s EDGxB and EDGxA
bits, both the input capture and input capture holding register are
considered empty. The first valid edge received after enabling a
channel will latch the ECT’s free running counter into the input
capture register (TCx) without setting the channel’s associated CxF
interrupt flag. The second valid edge received will transfer the value
of the input capture register, TCx, into the channel’s TCxH holding
register, latch the current value of the free running timer into the
input capture register and set the channel’s associated CxF interrupt
flag. In this condition, both the TCx and TCxH registers are
considered ‘full’.

If a corresponding channel’s NOVWx bit in the ICOVW register is set,
the capture register or its holding register cannot be written by a
valid edge at the input pin unless they are first emptied by reading
the TCx and TCxH registers. The act of reading the TCx and TCxH
registers and clearing the channel’s associated CxF interrupt flag
involves three separate operations. Two 16-bit read operations and an 8-
bit write operation.

If a channel’s associated CxF interrupt flag is cleared before reading
the TCx and TCxH registers and if a valid input edge occurs during or
between the reading of the capture and holding register, a channel’s
associated CxF interrupt flag will no longer be set as the result of
valid input edges. For example:

Clear CxF
|
|
V
Read TCx <----+
| |
|<--------+--- Valid Input Edge Occurs
V |
Read TCxH <---+

If the TCx and TCxH registers are read before a channel’s associated
CxF interrupt flag is cleared and if a valid input edge occurs between
the reading of TCx/TCxH and the clearing of a channel’s associated CxF
interrupt flag, a channel’s associated CxF interrupt flag will no
longer be set as the result of valid input edges. For example:

Clear CxF
|
|
V
Read TCx
|
|<------------ Valid Input Edge Occurs
V
Read TCxH


Systems that service the interrupt request and read the TCx and TCxH
registers before the next valid edge occurs at a channel’s associated
input pin will avoid the conditions under which the errata will occur.

Workaround


A simple workaround exists for this errata:


1. Clear the input capture channel’s associated CxF bit.
2. Disable the input capture function by writing 0:0 to a channel’s
EDGxB and EDGxA bits.
3. Read TCx
4. Read TCxH
5. Re-enable the input capture function by writing to a channel’s EDGxB
and EDGxA bits.


Code Example:

unsigned char ICSave;
unsigned int TC0Val;
unsigned int TC0HVal;

ICSave = TCTL4 & 0x03; /* save state of EDG0B and EDG0A */
TFLG1 = 0x01; /* clear ECT Channel 0 flag */
TCTL4 &= 0xfc; /* disable Channel 0 input capture function */
TC0Val = TC0; /* Read value of TC0 */
TC0HVal = TC0H; /* Read value of TC0H */
TCTL4 |= ICSave; /* Restore Channel 0 input capture function */



ECT_16B8C: Output compare pulse is inaccurateMUCts04151

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.06 (28

Apr 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.







PWM: Wrong output value after restart from stop or wait modeMUCts04199

Description

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.



Workaround


Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04203

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.


Workaround


If emergency shutdown mode is required:


In 16-bit concatenation mode, user can disable the related PWM
channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




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