Device Errata 68330 Integrated CPU32 Processor 2/6/95 This errata list applies to the following 68330 mask sets: Mask Processing Part Number Geometry Suffix E84J 0.8u A The mask set for each part is encoded into the device topside markings - for example, the following markings would indicate a device from the 1D81H mask, manufactured in the 12th week of 1994: XC68330FC16 1D81H QEAQ9412 The errata are organized by mask set, from oldest to newest, with each errata listed under the last mask set that it applies to. When working with rev. B silicon, for instance, the errata for all prior revisions 0- A do not apply - the errata shown for revisions B and later do apply (unless otherwise specifically noted). The above mask list does not include masks which were never released to production or sampled. =============== Mask: E84J =============== 1. SIM: Loss of Crystal without Limp Mode Q If there is a loss of crystal and the VCO is set to a low operating frequency (131 KHz), the part may lock up and not enter limp mode. This condition is most noticeable at high VCC and cold temperatures (-40 !C). 2. CPU: System Clock Minimum Frequency: The minimum operating frequency for external clock without PLL mode is 100kHz. 3. SIM: External Clock with VCO mode - When using external clock with VCO mode, with an XFC capacitor in the 0.01-0.1uF range, the SIM may not reliably detect VCO lock on powerup. As a result, the part never releases RESET even though the EXTAL input clock and CLKOUT are in phase. Workaround: Use a smaller XFC capacitor - for frequencies > 1MHz start with a capacitance value of 10000pf/F_MHz. Example: for 16.0MHz the recommended XFC capacitance is approximately = 10000pf/16.0 = 625pf. An external POR circuit should be used for all external clock applications to guarantee RESET remains asserted until after VCC stabilizes. 4. LPSTOP and External Clock with VCO: When using external clock with VCO mode, the CPU will not reliably exit LPSTOP if the SYNCR is programmed to turn off the VCO when in LPSTOP. Workaround: Program the SYNCR to enable the VCO in LPSTOP. 5. SIM: Autovectored IACK and BR: If BR is asserted during an autovectored IACK cycle, AS will negate 1/2 clock early. Workaround: Decode the IACK address range (A19 & FC2 & FC1 & FC0 & !AS) and use the resulting signal to force BR high during IACK cycles. 6. SIM: Show Cycles and BR: If show cycles and external arbitration are enabled, and BR is asserted immediately before the clock edge from which DS asserts for a show cycle, the show cycle will be truncated. The data bus drive time for the show cycle will overlap the front end of the alternate master bus tenure by one clock (data will tristate from the clock falling edge one clock after the falling edge BG asserts from). Workarounds: 1) Disable show cycles when alternate master bus activity is possible. 2) Delay BG assertion to the system by one clock, or delay the alternate master from driving the data bus for one clock after BG asserts. ____________________________________________________________ 68330 Integrated Processor NOTES These notes describe silicon operation which is different from the original documented operation of the 68330. These are permanent features - future documentation revisions will reflect this operation. 1. PIT, Background Mode Q If Background Debug Mode is entered and exited while the PIT is running and the FRZ1 bit in the SIM MCR is set, the PIT value may decrement by an extra count, shortening the timeout period. This will typically only affect emulation. 2. VCCSYN Power Q VCCSYN provides power to the VCC pin when the part is powered down. Power VCCSYN from the same supply as VCC, with appropriate filtering as shown in the manual. 3. The tDICL (min.) specification #27 has been changed from 5ns (min.) to 8ns (min.) on the MC68330FC16VA and MC68330PV16VA only. Effective mask: E84J (rev A). 4. The silicon revisions prior to E84J released the CPU from a power-on reset when VCO lock was detected; this has been replaced with a fixed delay of 328 input clock cycles. This delay does not occur for external clock without PLL mode. Effective mask: E84J (rev A). 5. LPSTOP operation was changed. In prior silicon revisions, the CPU exits from LPSTOP when VCO lock is detected; this has been replaced with a fixed delay of328 input clock cycles. This delay does not apply when the PLL is disabled (external clock without PLL mode), or when the VCO is allowed to operate during LPSTOP (by setting the STSIM bit of the SYNCR register). Effective mask: E84J (rev A). 6. JTAG I/O control change. Following JTAG test reset (not functional reset), all I/O and output pins will be set to input or high-impedance states. This was not previously true for some pins. Note that most automated vector generators (and most programmers) don't rely on the reset to determine their direction anyway. Effective mask: E84J (rev A). ---------------------------- * indicates an active-low signal